M2V28S20TP View Datasheet(PDF) - Mitsumi
Part Name
Description
Manufacturer
M2V28S20TP Datasheet PDF : 52 Pages
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SDRAM (Rev. 1.0E)
Jun. '99
MITSUBISHI LSIs
M2V28S20TP-6,-7,-8
M2V28S30TP-6,-7,-7L,-8,-8L
M2V28S40TP-7,-7L,-8,-8L
128M Synchronous DRAM
(4-BANK x 8,388,608-WORD x 4-BIT)
(4-BANK x 4,194,304-WORD x 8-BIT)
(4-BANK x 2,097,152-WORD x 16-BIT)
[ Write Interrupted by Write ]
Burst write operation can be interrupted by new write of any bank. Random column access is
allowed. WRITE to WRITE interval is minimum 1 CLK.
Write Interrupted by Write (BL=4)
CLK
Command
Write Write
Write
Write
A0-9
Yi Yj
Yk
Yl
A10
0
0
0
0
A11
BA0,1
00 00
10
00
DQ
Dai0 Daj0 Daj1 Dbk0 Dbk1 Dbk2 Dal0 Dal1 Dal2 Dal3
[ Write Interrupted by Read ]
Burst write operation can be interrupted by read of the same or the other bank. Random
column access is allowed. WRITE to READ interval is minimum 1 CLK. The input data on DQ at the
interrupting READ cycle is "don't care".
Write Interrupted by Read (BL=4, CL=3)
CLK
Command
Write READ
Write
READ
A0-9
Yi Yj
Yk
Yl
A10
0
0
0
0
A11
BA0,1
00 00
10
00
DQM
DQ
Dai0
Qaj0 Qaj1
Dbk0 Dbk1
Qal0
MITSUBISHI ELECTRIC
23
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