M2V28S20TP View Datasheet(PDF) - Mitsumi

Part Name

Description

Manufacturer

M2V28S20TP

128M Synchronous DRAM

Mitsumi 

SDRAM (Rev. 1.0E)

Jun. '99

MITSUBISHI LSIs

M2V28S20TP-6,-7,-8

M2V28S30TP-6,-7,-7L,-8,-8L

M2V28S40TP-7,-7L,-8,-8L

128M Synchronous DRAM

(4-BANK x 8,388,608-WORD x 4-BIT)

(4-BANK x 4,194,304-WORD x 8-BIT)

(4-BANK x 2,097,152-WORD x 16-BIT)

[ Write Interrupted by Precharge ]

Burst write operation can be interrupted by precharge of the same bank. Random column

access is allowed. Write recovery time (tWR) is required from the last data to PRE command.

Write Interrupted by Precharge (BL=4)

CLK

Command

A0-9

A10

Write

PRE

tWR

tRP

Yi

0

0

ACT

Xb

Xb

A11

Xb

BA0,1

00

00

00

DQM

DQ

Dai0 Dai1 Dai2

MITSUBISHI ELECTRIC

24

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