MPC8544E(2009) View Datasheet(PDF) - Freescale Semiconductor

Part Name

Description

Manufacturer

MPC8544E
(Rev.:2009)

PowerQUICC™ III Integrated Processor Hardware Specifications

Freescale Semiconductor 

Input Clocks

It is imperative to note that the processor’s minimum and maximum SYSCLK, core, and VCO frequencies

must not be exceeded regardless of the type of clock source. Therefore, systems in which the processor is

operated at its maximum rated e500 core frequency should avoid violating the stated limits by using

down-spreading only.

4.2 Real-Time Clock Timing

The RTC input is sampled by the platform clock (CCB clock). The output of the sampling latch is then

used as an input to the counters of the PIC and the TimeBase unit of the e500. There is no jitter

specification. The minimum pulse width of the RTC signal should be greater than 2 × the period of the

CCB clock. That is, minimum clock high time is 2 × tCCB, and minimum clock low time is 2 × tCCB. There

is no minimum RTC frequency; RTC may be grounded if not needed.

4.3 eTSEC Gigabit Reference Clock Timing

Table 7 provides the eTSEC gigabit reference clocks (EC_GTX_CLK125) AC timing specifications for

the MPC8544E.

Table 7. EC_GTX_CLK125 AC Timing Specifications

Parameter/Condition

Symbol

Min

Typ

Max

Unit Notes

EC_GTX_CLK125 frequency

fG125

—

EC_GTX_CLK125 cycle time

tG125

—

EC_GTX_CLK rise and fall time

LVDD, TVDD = 2.5 V

LVDD, TVDD = 3.3 V

tG125R/tG125F

—

EC_GTX_CLK125 duty cycle

tG125H/tG125

GMII, TBI

45

1000Base-T for RGMII, RTBI

47

125

—

MHz

—

8

—

ns

—

—

ns

1

0.75

1.0

—

%

2

55

53

Notes:

1. Rise and fall times for EC_GTX_CLK125 are measured from 0.5 and 2.0 V for L/TVDD = 2.5 V, and from 0.6 and 2.7 V for

L/TVDD = 3.3 V.

2. EC_GTX_CLK125 is used to generate the GTX clock for the eTSEC transmitter with 2% degradation. EC_GTX_CLK125

duty cycle can be loosened from 47%/53% as long as the PHY device can tolerate the duty cycle generated by the eTSEC

GTX_CLK. See Section 8.7.4, “RGMII and RTBI AC Timing Specifications,” for duty cycle for 10Base-T and 100Base-T

reference clock.

4.4 Platform to FIFO Restrictions

Please note the following FIFO maximum speed restrictions based on platform speed.

For FIFO GMII mode:

FIFO TX/RX clock frequency ≤ platform clock frequency ÷ 4.2

For example, if the platform frequency is 533 MHz, the FIFO Tx/Rx clock frequency should be no more

than 127 MHz.

MPC8544E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 3

Freescale Semiconductor

15

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