MPC8544E(2009) View Datasheet(PDF) - Freescale Semiconductor

Part Name

Description

Manufacturer

MPC8544E
(Rev.:2009)

PowerQUICC™ III Integrated Processor Hardware Specifications

Freescale Semiconductor 

RESET Initialization

For FIFO encoded mode:

FIFO TX/RX clock frequency ≤ platform clock frequency ÷ 3.2

For example, if the platform frequency is 533 MHz, the FIFO Tx/Rx clock frequency should be no more

than 167 MHz.

4.5 Other Input Clocks

For information on the input clocks of other functional blocks of the platform such as SerDes, and eTSEC,

see the specific section of this document.

5 RESET Initialization

This section describes the AC electrical specifications for the RESET initialization timing requirements of

the MPC8544E. Table 8 provides the RESET initialization AC timing specifications for the DDR SDRAM

component(s).

Table 8. RESET Initialization Timing Specifications1

Parameter/Condition

Min

Required assertion time of HREST

100

Minimum assertion time for SRESET

3

PLL input setup time with stable SYSCLK before HRESET

100

negation

Input setup time for POR configs (other than PLL config) with

4

respect to negation of HRESET

Input hold time for all POR configs (including PLL config) with

2

respect to negation of HRESET

Maximum valid-to-high impedance time for actively driven POR

—

configs with respect to negation of HRESET

Note:

1. SYSCLK is the primary clock input for the MPC8544E.

Max

Unit

Notes

—

μs

—

—

SYSCLKs

1

—

μs

—

—

SYSCLKs

1

—

SYSCLKs

1

5

SYSCLKs

1

Table 9 provides the PLL lock times.

Table 9. PLL Lock Times

Parameter/Condition

Core and platform PLL lock times

Local bus PLL

PCI bus lock time

Min

Max

Unit Notes

—

100

μs

—

—

50

μs

—

—

50

μs

—

MPC8544E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 3

16

Freescale Semiconductor

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