MT41J128M View Datasheet(PDF) - Micron Technology

Part Name

Description

Manufacturer

MT41J128M

DDR3 SDRAM

Micron Technology 

State Diagram

1Gb: x4, x8, x16 DDR3 SDRAM

State Diagram

Figure 2: Simplified State Diagram

Power

applied

Power

on

Reset

procedure

From any

state

RESET

Initial-

ization

ZQCL

MRS, MPR,

write

leveling

MRS

ZQ

ZQCL/ZQCS

calibration

Idle

SRE

SRX

REF

CKE L

Self

refresh

Refreshing

Active

power-

down

PDX

CKE L

PDE

PDE

ACT

PDX

Activating

Precharge

power-

down

CKE L

WRITE

Writing

WRITE

Bank

active

READ

WRITE AP

WRITE

READ AP

READ

READ

Reading

WRITE AP

Writing

WRITE AP READ AP

PRE, PREA

PRE, PREA

PRE, PREA

READ AP

Reading

ACT = ACTIVATE

MPR = Multipurpose register

MRS = Mode register set

PDE = Power-down entry

PDX = Power-down exit

PRE = PRECHARGE

PDF: 09005aef826aa906

1Gb_DDR3_SDRAM.pdf - Rev. L 03/13 EN

Precharging

PREA = PRECHARGE ALL

READ = RD, RDS4, RDS8

READ AP = RDAP, RDAPS4, RDAPS8

REF = REFRESH

RESET = START RESET PROCEDURE

SRE = Self refresh entry

Automatic

sequence

Command

sequence

SRX = Self refresh exit

WRITE = WR, WRS4, WRS8

WRITE AP = WRAP, WRAPS4, WRAPS8

ZQCL = ZQ LONG CALIBRATION

ZQCS = ZQ SHORT CALIBRATION

11

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