MT48LC1M16A1 View Datasheet(PDF) - Micron Technology
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Description
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MT48LC1M16A1 Datasheet PDF : 51 Pages
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CLOCK SUSPEND
The clock suspend mode occurs when a column
access/burst is in progress and CKE is registered LOW. In
the clock suspend mode, the internal clock is deacti-
vated, “freezing” the synchronous logic.
For each positive clock edge on which CKE is sampled
LOW, the next internal positive clock edge is sus-
pended. Any command or data present on the input
pins at the time of a suspended internal clock edge are
ignored; any data present on the DQ pins will remain
driven; and burst counters are not incremented as long
as the clock is suspended (see examples in Figures 22
and 23).
16Mb: x16
IT SDRAM
Clock suspend mode is exited by registering CKE
HIGH; the internal clock and related operation will
resume on the subsequent positive clock edge.
BURST READ/SINGLE WRITE
The burst read/single write mode is entered by pro-
gramming the write burst mode bit (M9) in the Mode
Register to a logic 1. In this mode, all WRITE com-
mands result in the access of a single column location
(burst of one) regardless of the programmed burst
length. READ commands access columns according to
the programmed burst length and sequence, just as in
the normal mode of operation (M9 = 0).
T0
T1
T2
T3
CLK
T4
T5
CKE
INTERNAL
CLOCK
COMMAND
NOP
WRITE
NOP
NOP
ADDRESS
BANK,
COL n
DQ
DIN
n
DIN
n+1
DIN
n+2
NOTE: For this example, burst length = 4 or greater, and DQM
is LOW.
Figure 22
Clock Suspend During WRITE Burst
T0
T1
T2
T3
T4
T5
T6
CLK
CKE
INTERNAL
CLOCK
COMMAND
READ
NOP
NOP
NOP
NOP
NOP
ADDRESS
BANK,
COL n
DQ
DOUT
n
DOUT
n+1
DOUT
n+2
DOUT
n+3
NOTE: For this example, CAS latency = 2, burst length = 4 or greater, and
DQM is LOW.
DON’T CARE
Figure 23
Clock Suspend During READ Burst
16Mb: x16 IT SDRAM
16MSDRAMx16IT.p65 – Rev. 5/99
22
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999, Micron Technology, Inc.
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