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MT48LC1M16A1 View Datasheet(PDF) - Micron Technology

Part Name
Description
Manufacturer
MT48LC1M16A1
Micron
Micron Technology Micron
MT48LC1M16A1 Datasheet PDF : 51 Pages
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CONCURRENT AUTO PRECHARGE
An access command (READ or WRITE) to another
bank while an access command with AUTO
PRECHARGE enabled is executing is not allowed by
SDRAMs, unless the SDRAM supports CONCURRENT
AUTO PRECHARGE. Micron SDRAMs support CON-
CURRENT AUTO PRECHARGE. Four cases where
CONCURRENT AUTO PRECHARGE occurs are de-
fined below.
READ with AUTO PRECHARGE
1. Interrupted by a READ (with or without AUTO
16Mb: x16
IT SDRAM
PRECHARGE): A READ to bank m will interrupt a
READ on bank n, CAS latency later. The
PRECHARGE to bank n will begin when the READ
to bank m is registered (Figure 24).
2. Interrupted by a WRITE (with or without AUTO
PRECHARGE): A WRITE to bank m will interrupt a
READ on bank n when registered. DQM should be
used two clocks prior to the WRITE command to
prevent bus contention. The PRECHARGE to bank
n will begin when the WRITE to bank m is registered
(Figure 25).
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
NOP
READ - AP
BANK n
NOP
READ - AP
BANK m
NOP
NOP
BANK n
Internal
States
BANK m
Page Active
READ with Burst of 4
Page Active
Interrupt Burst, Precharge
t RP - BANK n
READ with Burst of 4
NOP
NOP
Idle
tRP - BANK m
Precharge
ADDRESS
BANK n,
COL a
BANK m,
COL d
DQ
DOUT
a
DOUT
a+1
DOUT
d
DOUT
d+1
CAS Latency = 3 (BANK n)
NOTE: DQM is LOW.
CAS Latency = 3 (BANK m)
Figure 24
READ with AUTO PRECHARGE Interrupted by a READ
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
READ - AP
BANK n
NOP
NOP
Internal
BANK n
Page
Active
READ with Burst of 4
States
BANK m
Page Active
NOP
WRITE - AP
BANK m
NOP
NOP
Interrupt Burst, Precharge
tRP - BANK n
WRITE with Burst of 4
NOP
Idle
t WR - BANK m
Write-Back
ADDRESS
1
DQM
BANK n,
COL a
BANK m,
COL d
DQ
DOUT
DIN
a
d
DIN
d+1
DIN
d+2
DIN
d+3
CAS Latency = 3 (BANK n)
NOTE: 1. DQM is HIGH at T2 to prevent DOUT-a+1 from contending with DIN-d at T4.
DONT CARE
Figure 25
READ with AUTO PRECHARGE Interrupted by a WRITE
16Mb: x16 IT SDRAM
16MSDRAMx16IT.p65 Rev. 5/99
23
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999, Micron Technology, Inc.

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