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QT1100A-ISG View Datasheet(PDF) - Quantum Research Group

Part Name
Description
Manufacturer
QT1100A-ISG
Quantum
Quantum Research Group Quantum
QT1100A-ISG Datasheet PDF : 42 Pages
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former can occur if the Cs capacitor fails or there is a short
in the SNS circuit; if this happens, the affected key is shut
down immediately and the key is switched off.
Keys that are intentionally disabled will not burst, and so
cannot show an error. In standalone mode with no EEPROM
present (Scanport mode), keys are disabled by strapping the
SNS pins to ‘unused’ settings (Table 1.1 page 4), and this
will not generate a ‘major error’, unless the error occurs after
the part has gone through power-up calibration successfully
without detecting that the key is disabled via SNS pin
configuration.
In any mode that uses an EEPROM or uses either UART or
SPI communications, keys must be disabled by setting the
NTHR parameter to zero for the key(s) (Section 4.1). If in
EEPROM or serial mode a key is disabled via SNS pin wiring
only, it will be classified as a ‘major error’.
control. The UART mode operates in the same way and with
the same protocol and commands as the SPI interface.
UART mode is selected by strapping the CMODE pin low.
UART mode and Scanport mode can operate together. If
only UART mode is desired, the Scan_In pins need to be
grounded. If only the Scanport is used, the UART can be
ignored. An unused RX line should be connected directly to
Vdd.
UART transmission parameters are (Fosc = 12MHz):
Baud rate options:
Start bits:
Data bits:
Parity:
Stop bits:
4800, 9600, 19.2K, 28.8K
1
8
None
1
UART Operation with Scanport: Scanport and UART
operation can be used together. (See Section 2.14)
3 Serial Operation
There are two serial interfaces in the QT1100A: UART, and
SPI.
UART provides a simple solution using well known
asynchronous signalling. Many MCUs contain UART or
USART blocks which are perfectly suited to this mode.
MCUs without a UART hardware function can easily use a
firmware UART function in most cases. The chief advantage
of UART mode is wiring simplicity: only 3 wires, (TX, RX, and
CRDY) are required.
SPI communications are based on the well known
synchronous interface used extensively between
microcontrollers and peripherals. The QT1100A uses
slave-only SPI mode. This interface does not require an
accurate clock rate, and can operate faster than UART
mode. However, SPI operation requires 5 wires.
The host device always initiates communications
sequences; the QT1100A is incapable of chattering data
back to the host. A command from the host to the QT1100A
always ends in a one or more byte response from the
QT1100A. Some transmission types from the host require
the use of a CRC check byte to provide for robust
communications. This command/response design is
intentional for FMEA purposes so that the host always has
total control over the communications with the QT1100A.
Effectively this behavior forces designs to have inherently
self-checking ‘loop back’ characteristics.
System Response Time: The setting of the two detection
integrators (see Section 4.9) strongly affects the basic
device response time. The serial poll rate adds to this
response time. If the basic QT1100A response time is 80ms,
and the host polls the device every 50ms, the total response
time can be a very slow 130ms. Normally, the host should
poll the QT1100A every ~10ms to minimize delay ‘stacking’.
To minimize delays further, the command 0xC9 can be used
(‘Quick 1st Key’; see Section 3.5.14) instead of 0xC0.
One way to improve speed while minimizing host activity is
to have the host monitor the LED/STAT pin, perhaps via
interrupt, and service the device with a 0xC0 or 0xC9
command only when the LED/STAT pin becomes active.
(See Section 4.8)
3.1 UART Interface
UART mode allows a host device to communicate
conveniently over two serial wires asynchronously, with a
handshaking line (CRDY) to provide bidirectional data flow
3.1.1 TX Pin
The TX pin has an open-drain drive to allow bussing with
other similar parts. The TX line can thus be shared with other
UART based peripherals such as a second QT1100A.
TX must be pulled high to Vdd with a resistor in UART mode.
The resistor value will depend on the total amount of stray
capacitance on TX - more capacitance will require lower
values of pull-up resistor, especially at higher Baud rates.
The risetime of the signals on this line should be 1/10th of
the bit width, i.e., if running at 9600 Baud, the bit width is
about 100µs, and the risetime should be 10µs or less. In
most cases, a 47K resistor is low enough, however this
should be confirmed using an oscilloscope.
An unused TX pin should be connected to Vss.
3.1.2 Sleep/Wake Operation in UART Mode
The device can be put into sleep mode with a serial
command (0x05). The device can sleep for up to 700ms;
some time after this it will self-reset. The Wake and RX
functions are on the same pin, which allows a host to
conveniently wake the device with a dummy character (e.g.
0x00 null) before communicating with it. Wake operates on
the falling edge; the negative-going level must be at least
40µs wide to be recognized.
See also Section 3.4.6.
3.1.3 CRDY Operation in UART Mode
The CRDY serial handshake pin is open-drain and requires a
10K ~ 220K pull-up to Vdd. Either the host or the QT1100A
can pull down on this line to stop data flow (wire d-AND
logic). If CRDY is high the communications can flow in either
direction. The host should obey this control line or overruns
and transmission errors will occur in the device.
Host-to-QT1100A UART CRDY Behavior: If the CRDY line
is released by the host but the CRDY line stays low, this
means the QT1100A is busy and cannot accept
communications. The host must wait for the CRDY line to
float high again before it can send the byte. If the CRDY line
happens to go low again just as the host is about to send a
byte, the host has a 10µs grace period in which it can still
initiate the transmission. This is acceptable for most MCU
types, however even fast PCs operating under Windows
have a difficult time responding within the 10µs grace period
and this can result in frequent transmission errors.
QT1100A-to-Host UART CRDY Behavior: When the
QT1100A needs to send data back to the host, it will release
the CRDY line (if not already released) and wait for it to float
LQ
15
Copyright © 2003-2005 QRG Ltd
QT1100A-ISG R3.02/1105

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