QT1100A-ISG View Datasheet(PDF) - Quantum Research Group
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QT1100A-ISG Datasheet PDF : 42 Pages
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high before sending a byte. If the host is busy and cannot
accept data, it should clamp CRDY low until it is ready.
Before each return byte is sent, the QT1100A will check
CRDY in this manner and wait until the host is ready before
sending.
The host should allow a 10µs grace period in which it can
still accept data from the QT1100A after it releases CRDY
high, to allow for any delays in the response from the sensor.
CRDY / Burst Behavior: The pacing of CRDY and the
transmission of UART data are interleaved with acquisition
bursts. The QT1100A cannot send or receive data during a
burst or for a short time thereafter. CRDY is forced low by
the QT1100A when a burst is taking place and
communication is not possible. At the fastest burst spacing,
there is at least a 250µs window of time between bursts
when communications can take place and CRDY is high.
If a serial transmission from QT1100A to host is occurring
when a burst should be starting, the communications takes
precedence and the next acquisition burst is delayed.
3.2 SPI Operation
Refer to page 38 for timing diagram.
The SPI mode allows a host device to communicate
conveniently using four control lines synchronously, with a
CRDY handshaking line to provide control flow. The SPI
mode operates in the same way and with the same protocol
and commands as the UART interface. However whereas
the UART mode permits the QT1100A to send back
responses to the host under its own volition, the SPI mode is
a slave mode only requiring the host to always generate the
shift clock.
Where a response is expected back from the QT1100A, the
host can shift over a dummy null (0x00) command to the
QT1100A which will be ignored. The host should not overlap
commands with responses. Thus, if there are two expected
response bytes to a command, the host can send and shift
back the following bytes:
Shift # Host
QT1100A Response
1 Command_A 0x55 (see below*)
2 Null
Response_1 to A
3 Null
Response_2 to A
4 Command_B 0x55 (see below*)
SPI transmission parameters are (Fosc = 12MHz):
Transmission mode:
Clock rate:
Clock duty cycle:
Data bits:
Clock idle:
Clock shift out edge:
Clock shift in edge:
Delay from shift in edge:
Slave-only
100kHz max
50%
8
High
Falling
Rising
None
*Note that the QT1100A returns a 0x55 dummy byte with a
host command.
If a command is not recognized, the response on the next
shift will be 0x55.
3.2.1 Multi-Drop SPI Capability
In SPI mode the DO pin floats while /SS is high to allow the
SPI lines to be shared with other devices. A 10K ~ 20K Ohm
pull-up resistor should be used on this pin to prevent DO
from freely floating.
When used with other similar devices, each QT1100A part
should have its own /SS and CRDY connections back to the
host controller; the other SPI lines can all be shared.
3.2.2 Sleep/Wake Operation in SPI Mode
The device can be put into sleep mode with a serial
command (0x05). The device can sleep for up to 700ms;
some time after this it will self-reset. Wake operates on the
falling edge; the negative-going level must be at least 40µs
wide to be recognized.
The Wake pin can be connected to /SS, and the host can
then wake the device from sleep using a >40µs negative
dummy pulse on /SS.
See also Section 3.4.6.
3.2.3 CRDY Operation in SPI Mode
CRDY is an open-drain line requiring a 10K ~ 220K Ohm
pull-up resistor. The QT1100A will pull down on this line to
stop data flow from the host. The QT1100A does not
respond to the host pulling CRDY low in SPI mode, since the
host is always in control of all data transmissions. CRDY is
unidirectional (QT1100A to Host) in SPI mode.
The host must wait for CRDY to float high before it can clock
the SPI interface. If CRDY happens to go low again just as
the host is about to clock data, the host has a 10µs grace
period in which it can still initiate /SS (slave select) even
though CRDY has already gone low.
CRDY / Burst Behavior: The pacing of CRDY and the
transmission of UART data are interleaved with acquisition
bursts. The QT1100A cannot send or receive data during a
burst or for a short time thereafter.
CRDY is forced low by the QT1100A when a burst is taking
place and communication is not possible. At the fastest burst
spacing, there is at least a 250µs window of time between
bursts when communications can take place and CRDY is
high. Similarly, if the burst duration exceeds its timeslot, the
device will ensure that there is an additional 250µs
appended to the burst to allow for communications.
If a serial transmission is occurring when a burst should be
starting, the communication takes precedence and the next
acquisition burst is delayed. Therefore, the 250µs should be
viewed as a minimum which can expand to meet the needs
of a single byte transmission. Additional bytes will usually
occur in the next timeslot.
3.3 Communication Error Handling
If a communications error takes place, the host should
recover by issuing a ‘Return Last Command’ command
(0xC7) at least twice to make sure the QT1100A and host
are communicating properly with each other.
3.4 Control Commands
Control commands are used to place the device into special
modes or cause the device to reset, calibrate or run. (See
summary Table 3-1, page 23)
3.4.1 Null Command - 0x00 (SPI Only)
This command is used primarily to shift back data from the
QT1100A in SPI mode. Where a response is expected back
from the QT1100A after a command, the host should shift
over a null for each expected byte.
LQ
16
Copyright © 2003-2005 QRG Ltd
QT1100A-ISG R3.02/1105
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