QT1100A-ISG View Datasheet(PDF) - Quantum Research Group
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QT1100A-ISG Datasheet PDF : 42 Pages
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Since the host device is always the master in SPI mode, and
data are clocked in both directions, the null command is
required to act as a placeholder where the requirement is to
get data back from the QT1100A. See also Section 3.2.
In UART mode there is no response whatsoever to a null
command.
3.4.2 Enter Setups Load Mode - 0x01
This command is used to load the Setups block into the
device over either serial interface. See Table 4-1 on page 31
for reference.
The command must be repeated 2 times within 100ms or the
command will be aborted (not reset); the repeat of the
command must be sequential without any other intervening
command or even a null.
250µs worst case after receipt of the second 0x01, the
device will start to send back the response byte 0x53
(signalled using CRDY as always, i.e. the response could be
delayed beyond 250µs by the host itself, either via a late
shift operation in SPI Mode or via holding CRDY low in
UART mode).
If no 0x53 is returned, the command was not properly
received; the host should recover by issuing a ‘Return Last
Command’ command (0xC7) at least twice to make sure the
QT1100A and host are communicating properly with each
other, and then the 0x01 commands should be sent again.
From this point on the host should send the Setups block
including the ending CRC byte as a stream to the QT1100A,
without interruption, paced only by the CRDY line. During
this time the chip suspends its normal acquisition bursts.
The time between bytes can be from 10µs to a limit of
100ms.
If a data timeout occurred in the block load (the time
between any two sequential block data bytes exceeded
100ms) a response of 0xF1 will immediately be attempted
back to the host, the Setup block sequence will be aborted,
and the chip will reload the Setup block from the EEPROM
(if available and correct) or from ‘factory defaults’. A device
reset will automatically occur if the QT1100A does not
receive a further command (any of 0x01, 0x02, 0x03 or
0x04) within 1s after the block sequence has suspended due
to a timeout error.
The host should listen for a 0xF1 response while shifting the
Setups block to terminate and restart the Setups load
sequence if required.
Note that in SPI mode, all responses must be shifted out
with nulls shifted over by the host.
EEPROM not present: If no EEPROM is installed and DIEE
is tied to Vdd, the QT1100A will check the CRC and reply
with a response byte:
0xF0 - CRC not OK, and as a result block load failed
0xF1 - transfer timeout; time between bytes >100ms
0xFE - block loaded OK, CRC is OK
In the case of either 0xF0 or 0xF1, the QT1100A will load
‘factory defaults’ into the device (when no EEPROM is
present).
With no EEPROM present, the delay between the CRC byte
sent to the QT1100A and the response back from the
QT1100A is 800µs maximum (signalled using CRDY).
EEPROM present: With an EEPROM installed, the device
will check the CRC and if valid, start programming the
EEPROM with the new Setup block, and check that the
EEPROM is written correctly. It will respond as follows:
0xF0 - CRC is not OK, and as a result block load failed
0xF1 - transfer timeout; time between bytes >100ms
0xF2 - block loaded OK, but EEPROM write failed
0xFE - block loaded OK, CRC is OK, EEPROM write OK
(0xFE response requires up to 370ms due to
EEPROM write time - this is dependent largely on the
EEPROM’s write time specification)
If there is no response from the device within 370ms after
the block has been completely sent , the command was not
properly received and the device should preferably be reset
using the RST pin before attempting the command again.
Only if the entire Setup block is received without error and
the CRC is OK (or 0xD6 for testing; see below) will the
Setups information be recorded to EEPROM.
At the end of the full command sequence the device remains
suspended (acquire bursts are stopped) until a Setups, Run,
Cal, or Reset command is received (0x01, 0x02, 0x03, or
0x04). If one of these commands is not received within 1s
after the block is loaded and the response byte is generated ,
the part resets itself, enters Cal mode, and then runs
automatically.
If there was an error in the Setups load operation, the device
will run either with ‘factory defaults’ (if there was a 0xF2
error) or with previously stored EEPROM data (if there was a
0XF0 or 0xF1 error).
CRC Note: The 0x01 command requires that the ending
CRC byte is calculated by the host on the data block itself
without the 0x01 command itself being folded in to the CRC.
This is a notable exception to the use of CRCs in this device.
Other commands ending in a CRC fold in the command byte
itself as the first byte in the CRC calculation.
Dummy CRC for Testing: For testing purposes, a dummy
CRC byte, of value 0xD6, can be placed at the end of the
Setups block which is always accepted by the QT1100A
even though it is ‘wrong’. While a 0xD6 value will inhibit CRC
checking, the QT1100A will actually compute and record the
correct CRC value into the EEPROM (if present).
Should an actual CRC calculation result in a 0xD6
(probability = 0.39%) and CRC checking is required, the
designer should change one of the unused bits shown in the
Setup table (page 31) to cause the CRC to be something
else.
After a Setups Load: After a successful Setups block load,
there are four basic options:
1. Run the device via the 0x02 command, i.e. without the
benefit of a recalibration, or,
2. Calibrate the device via the 0x03 command, in which
case the device will calibrate all keys and run again, or,
3. Reset the device using the 0x04 command, or,
4. Wait 1 second for the device to enter self-reset.
Changes to NDCR, NRD, AKS, EK, K2L, PDCR, PRD,
PTHR, PHYS, LEDP, LBLL, KEYO, BR or BS do not require
a recalibration to take effect, and it is faster to just issue a
0x02 RUN command after the 0x01 is complete.
Changes to NTHR, NHYS, NDIL, FDIL, and NTM should be
followed with a 0x03 Cal command.
Changes to SE or SYNC should be followed with a device
reset command, RST pin reset, or 1s timeout reset to allow
the new parameters to properly take effect.
LQ
17
Copyright © 2003-2005 QRG Ltd
QT1100A-ISG R3.02/1105
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