S25FL127S View Datasheet(PDF) - Spansion Inc.
Part Name
Description
Manufacturer
S25FL127S Datasheet PDF : 131 Pages
| |||
Data Sheet (Preliminary)
2. Overview
2.1
General Description
The Spansion S25FL127S device is a flash non-volatile memory product using:
MirrorBit technology - that stores two data bits in each memory array transistor
Eclipse architecture - that dramatically improves program and erase performance
65 nm process lithography
This device connects to a host system via a Serial Peripheral Interface (SPI). Traditional SPI single bit serial
input and output (SIngle I/O or SIO) is supported as well as optional two bit (Dual I/O or DIO) and four bit
(Quad I/O or QIO) serial commands. This multiple width interface is called SPI Multi-I/O or MIO.
The Eclipse architecture features a Page Programming Buffer that allows up to 128 words (256 bytes) or
256 words (512 bytes) to be programmed in one operation, resulting in faster effective programming and
erase than prior generation SPI program or erase algorithms.
Executing code directly from flash memory is often called Execute-In-Place or XIP. By using FL-S devices at
the higher clock rates supported, with QIO command, the instruction read transfer rate can match or exceed
traditional parallel interface, asynchronous, NOR flash memories while reducing signal count dramatically.
The S25FL127S product offers a high density coupled with the flexibility and fast performance required by a
variety of embedded applications. It is ideal for code shadowing, XIP, and data storage.
April 25, 2013 S25FL127S_00_02
S25FL127S
11
Share Link: 