SiM3C1xx
Table 3.4. Reset and Supply Monitor
Parameter
VDD High Supply Monitor Threshold
(VDDHITHEN = 1)
VDD Low Supply Monitor Threshold
(VDDHITHEN = 0)
VREGIN Supply Monitor Threshold
Power-On Reset (POR) Threshold
VDD Ramp Time
Reset Delay from POR
Reset Delay from non-POR source
RESET Low Time to Generate Reset
Missing Clock Detector Response
Time (final rising edge to reset)
Missing Clock Detector Trigger
Frequency
VDD Supply Monitor Turn-On Time
Symbol
Test Condition
VVDDMH
Early Warning
Reset
VVDDML
Early Warning
Reset
VVREGM
VPOR
tRMP
tPOR
tRST
Early Warning
Rising Voltage on VDD
Falling Voltage on VDD
Time to VDD > 1.8 V
Relative to VDD >
VPOR
Time between release
of reset source and
code execution
tRSTL
tMCD
FAHB > 1 MHz
FMCD
tMON
Min
2.10
1.95
1.81
1.70
4.2
—
0.8
10
3
—
50
—
—
—
Typ
2.20
2.05
1.85
1.74
4.4
1.4
1
—
—
10
—
0.4
7.5
2
Max
2.30
2.1
1.88
1.77
4.6
—
1.3
3000
100
—
—
1
13
—
Unit
V
V
V
V
V
V
V
µs
ms
µs
ns
ms
kHz
µs
12
Rev.1.0