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SIM3C134 View Datasheet(PDF) - Silicon Laboratories

Part Name
Description
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SIM3C134 Datasheet PDF : 90 Pages
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SiM3C1xx
Table 3.10. SAR ADC
Parameter
Symbol
Test Condition
Min Typ Max Unit
Resolution
Nbits
12 Bit Mode
10 Bit Mode
12
Bits
10
Bits
Supply Voltage Requirements
(VDD)
VADC
High Speed Mode
Low Power Mode
2.2
3.6
V
1.8
3.6
V
Throughput Rate
(High Speed Mode)
fS
12 Bit Mode
250 ksps
10 Bit Mode
1
Msps
Throughput Rate
(Low Power Mode)
fS
12 Bit Mode
— 62.5 ksps
10 Bit Mode
250 ksps
Tracking Time
tTRK
High Speed Mode
230 —
ns
Low Power Mode
450 —
ns
SAR Clock Frequency
fSAR
High Speed Mode
— 16.24 MHz
Low Power Mode
4
MHz
Conversion Time
tCNV
10-Bit Conversion,
SAR Clock = 16 MHz,
APB Clock = 40 MHz
762.5
ns
Sample/Hold Capacitor
CSAR
Gain = 1
Gain = 0.5
5
pF
2.5
pF
Input Pin Capacitance
CIN
High Quality Inputs
18
pF
Normal Inputs
20
pF
Input Mux Impedance
RMUX
High Quality Inputs
Normal Inputs
— 300 —
— 550 —
Voltage Reference Range
Input Voltage Range1
VREF
VIN
Power Supply Rejection Ratio
DC Performance
Integral Nonlinearity
PSRRADC
INL
Gain = 1
Gain = 0.5
12 Bit Mode2
1
VDD
V
0
VREF
V
0
— 2xVREF V
70
dB
±1 ±1.9 LSB
10 Bit Mode
— ±0.2 ±0.5 LSB
Notes:
1. Absolute input pin voltage is limited by the lower of the supply at VDD and VIO.
2. INL and DNL specifications for 12-bit mode do not include the first or last four ADC codes.
3. The maximum code in 12-bit mode is 0xFFFC. The Slope Error is referenced from the maximum code.
Rev.1.0
17

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