ST10F273 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
ST10F273 Datasheet PDF : 179 Pages
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Memory organization
4
Memory organization
ST10F273
The memory space of the ST10F273 is configured in a unified memory architecture. Code
memory, data memory, registers and I/O ports are organized within the same linear address
space of 16 Mbytes. The entire memory space can be accessed Byte wise or Word wise.
Particular portions of the on-chip memory have additionally been made directly bit
addressable.
IFlash: 512 Kbytes of on-chip Flash memory. It is divided in 10 blocks (B0F0...B0F9) of the
Bank 0 and two blocks of Bank 1 (B1F0, B1F1): read-while-write operations inside the same
Bank are not allowed. When Bootstrap mode is selected, the Test-Flash Block B0TF
(8 Kbyte) appears at address 00’0000h: refer to Chapter 5: Internal Flash memory on
page 25 for more details on memory mapping in boot mode. The summary of address range
for IFlash is the following:
Table 2. Summary of IFlash address range
Blocks
User mode
Size
B0TF
Not visible
8K
B0F0
00’0000h - 00’1FFFh
8K
B0F1
00’2000h - 00’3FFFh
8K
B0F2
00’4000h - 00’5FFFh
8K
B0F3
00’6000h - 00’7FFFh
8K
B0F4
01’8000h - 01’FFFFh
32K
B0F5
02’0000h - 02’FFFFh
64K
B0F6
03’0000h - 03’FFFFh
64K
B0F7
04’0000h - 04’FFFFh
64K
B0F8
05’0000h - 05’FFFFh
64K
B0F9
06’0000h - 06’FFFFh
64K
B1F0
07’0000h - 07’FFFFh
64K
B1F1
08’0000h - 08’FFFFh
64K
IRAM: 2 Kbytes of on-chip internal RAM (dual-port) is provided as a storage for data,
system stack, general purpose register banks and code. A register bank is 16 Wordwide (R0
to R15) and / or Bytewide (RL0, RH0, …, RL7, RH7) general purpose registers group.
XRAM: 32 K + 2 Kbytes of on-chip extension RAM (single port XRAM) is provided as a
storage for data, user stack and code.
The XRAM is divided into two areas, the first 2 Kbytes named XRAM1 and the second
32 Kbytes named XRAM2, connected to the internal XBUS and are accessed like an
external memory in 16-bit demultiplexed bus-mode without wait state or read/write delay
(31.25ns access at 64 MHz CPU clock). Byte and Word accesses are allowed.
The XRAM1 address range is 00’E000h - 00’E7FFh if XPEN (bit 2 of SYSCON register),
and XRAM1EN (bit 2 of XPERCON register) are set. If XRAM1EN or XPEN is cleared, then
any access in the address range 00’E000h - 00’E7FFh will be directed to external memory
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