ST10F273 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
ST10F273 Datasheet PDF : 179 Pages
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Internal Flash memory
ST10F273
5.2.3
Note:
Table 6. Control register interface
Name
Description
FCR1-0
FDR1-0
FAR
FER
FNVWPIR
FNVAPR0
FNVAPR1
Flash control registers 1-0
Flash data registers 1-0
Flash address registers
Flash error register
Flash non volatile protection I
register
Flash Non volatile access
protection register 0
Flash non volatile access
protection register 1
Addresses
0x000E 0000 - 0x000E 0007
0x000E 0008 - 0x000E 000F
0x000E 0010 - 0x000E 0013
0x000E 0014 - 0x000E 0015
0x000E DFB4 - 0x000E DFB7
Size
Bus
size
8 byte
8 byte
4 byte
2 byte
16-bit
4 byte (XBUS)
0x000E DFB8 - 0x000E DFB9 2 byte
0x000E DFBC - 0x000E DFBF 4 byte
Low power mode
The Flash module is automatically switched off executing PWRDN instruction. The
consumption is drastically reduced, but exiting this state can require a long time (tPD).
Recovery time from Power down mode for the Flash modules is anyway shorter than the
main oscillator start-up time. To avoid any problem in restarting to fetch code from the Flash,
it is important to size properly the external circuit on RPD pin.
PWRDN instruction must not be executed while a Flash program/erase operation is in
progress.
5.3
Write operation
The Flash module have one single register interface mapped in the memory space 0x0E
0000 to 0x0E 0015. All the operations are enabled through four 16-bit control registers:
Flash Control Register 1-0 High/Low (FCR1H/L-FCR0H/L). Eight other 16-bit registers are
used to store Flash Address and Data for Program operations (FARH/L and FDR1H/L-
FDR0H/L) and Write Operation Error flags (FERH/L). All registers are accessible with 8 and
16-bit instructions (since operates in 16-bit mode when in read/ write).
Before accessing the Flash registers used for program/erasing operations, bit 5
(XFLASHEN) in XPERCON register shall be set.
The two banks have their own dedicated sense amplifiers, so that one bank can be read
while the other is written.
During a Flash write operation, any attempt to read the bank under modification will output
invalid data (software trap 009Bh). This means that the Flash bank is not fetchable when a
programming operation is active: The write operation commands must be executed from
another bank or from the other memory (internal RAM or external memory).
During a Write operation, when bit LOCK of FCR0 is set, it is forbidden to write into the
Flash Control Registers.
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