RM7000™ Microprocessor with On-Chip Secondary Cache Datasheet
Released
10.3 System Interface Parameters
CPU Speed
Parameter1 Symbol Test Conditions
200 MHz 250 MHz 266 MHz 300 MHz
Min Max Min Max Min Max Min Max Units
Data Output2,3 tDO
mode14..13 = 10 (fastest) 1.0 5.0 1.0 5.0 1.0 4.5 1.0 4.5 ns
mode14..13 = 11
1.0 5.5 1.0 5.5 1.0 5.0 1.0 4.5 ns
mode14..13 = 00
1.0 6.0 1.0 6.0 1.0 5.0 1.0 5.0 ns
mode14..13 = 01
(slowest)
1.0 7.0 1.0 6.5 1.0 6.0 1.0 5.5 ns
Data Setup4 tDS
trise = see above table 2.5
2.5
2.5
2.5
ns
Data Hold4
tDH
tfall = see above table
1.0
1.0
1.0
1.0
ns
Notes
1. Timings are measured from 0.425 x VccIO of clock to 0.425 x VccIO of signal for 3.3V I/O.
2. Capacitive load for all output timings is 50 pF.
3. Data Output timing applies to all signal pins whether tristate I/O or output only.
4. Setup and Hold parameters apply to all signal pins whether tristate I/O or input only.
5. Only mode 14:13 = 10 is tested and guaranteed.
10.4 Boot-Time Interface Parameters
Parameter7 Symbol
Mode Data
tDS
Setup
Mode Data Hold tDH
Test Condi-
tions
Min
4
0
Max
Units
SysClock cycles
SysClock cycles
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Document ID: PMC-2002175, Issue 1