RM7000-250T View Datasheet(PDF) - PMC-Sierra
Part Name
Description
Manufacturer
RM7000-250T Datasheet PDF : 54 Pages
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RM7000™ Microprocessor with On-Chip Secondary Cache Datasheet
Released
Figure 10 Processor Block Write
SysClock
SysAD
Addr Data0 Data1
SysCmd
Write NData NData
ValidOut*
ValidIn*
RdRdy*
WrRdy*
Release*
Data2 Data3
NData NEOD
Figure 11 Multiple Outstanding Reads
Master
Processor
SysClock
SysAD
SysCmd
Addr1
Read1
Tertiary(Miss)
System
Processor
2
5
Data0 Data1
Addr2
Read2
RspSwap*
ValidOut*
ValidIn*
Tertiary(Miss)
Data0 Data1
7
Release*
PRqst*
3
4
PAck*
1
6
TcMatch
System
Data02 Data12
NData NData
8
4.30 Data Prefetch
The RM7000 is the first PMC-Sierra design to support the MIPS IV integer data prefetch (PREF)
and floating-point data prefetch (PREFX) instructions. These instructions are used by the
compiler or by an assembly language programmer when it is known or suspected that an upcoming
data reference is going to miss in the cache. By appropriately placing a prefetch instruction, the
memory latency can be hidden under the execution of other instructions. If the execution of a
prefetch instruction would cause a memory management or address error exception the prefetch is
treated as a NOP.
Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use
31
Document ID: PMC-2002175, Issue 1
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