IT66121FN View Datasheet(PDF) - ITE Tech. INC.

Part Name

Description

Manufacturer

IT66121FN

Low Power Transmitter with HDMI1.4 3D

ITE Tech. INC. 

IT66121FN

up/down-sampling. Depending on the selected input and output video formats, different processing

blocks are either enabled or bypassed via register control. For the sake of flexibility, this is all done in

software register programming. Therefore, extra care should be taken in keeping the selected

input-output format combination and the corresponding video processing block selection. Please refer

to the IT66121 Programming Guide for suggested register setting.

Figure 3. Video data processing flow of IT66121

Designated as D[23:0], the input video data could take on bus width of 8 bits to 24 bits. This input

interface could be configured through register setting to provide various data formats as listed in Table

1.

Although not explicitly depicted in Figure 3, input video clock (PCLK) can be configured to be

multiplied by 0.5, 1, 2 or 4, so as to support special formats such as CCIR-656 and pixel-repeating.

This is also enabled by software programming.

General description of block functions is as follows:

Extraction of embedded control signals (Embedded Ctrl. Signals Extraction)

Input video formats with only embedded sync signals rely on this block to derive the proper Hsync,

Vsync and DE signals. Specifically, CCIR-656 video stream includes Start of Active Video (SAV) and

www.ite.com.tw

Nov-2011 Rev:0.99 8/39

Share Link: