MSC8122 View Datasheet(PDF) - Freescale Semiconductor

Part Name

Description

Manufacturer

MSC8122

Quad Digital Signal Processor

Freescale Semiconductor 

Electrical Characteristics

2.5.4.3 Reset Timing Tables

Table 12 and Figure 9 describe the reset timing for a reset configuration write through the direct slave interface (DSI) or

through the system bus.

Table 12. Timing for a Reset Configuration Write through the DSI or System Bus

No.

1

2

3

5

6

7

8

Note:

Characteristics

Required external PORESET duration minimum

• CLKIN = 20 MHz

• CLKIN = 100 MHz (300 MHz core)

• CLKIN = 133 MHz (400 MHz core)

• CLKIN = 166 MHz (500 MHz core)

Delay from deassertion of external PORESET to deassertion of internal

PORESET

• CLKIN = 20 MHz to 166 MHz

Delay from de-assertion of internal PORESET to SPLL lock

• CLKIN = 20 MHz (RDF = 1)

• CLKIN = 100 MHz (RDF = 1) (300 MHz core)

• CLKIN = 133 MHz (RDF = 2) (400 MHz core)

• CLKIN = 166 MHz (RDF = 2) (500 MHz core)

Delay from SPLL to HRESET deassertion

• REFCLK = 40 MHz to 166 MHz

Delay from SPLL lock to SRESET deassertion

• REFCLK = 40 MHz to 166 MHz

Setup time from assertion of RSTCONF, CNFGS, DSISYNC, DSI64,

CHIP_ID[0–3], BM[0–2], SWTE, and MODCK[1–2] before deassertion of

PORESET

Hold time from deassertion of PORESET to deassertion of RSTCONF,

CNFGS, DSISYNC, DSI64, CHIP_ID[0–3], BM[0–2], SWTE, and

MODCK[1–2]

Timings are not tested, but are guaranteed by design.

Expression

16/CLKIN

1024/CLKIN

6400/(CLKIN/RDF)

(PLL reference

clock-division factor)

512/REFCLK

515/REFCLK

Min Max

800

—

160

—

120

—

96

—

6.17

51.2

320

320

64

64

96

96

77

77

3.08

12.8

3.10 12.88

3

—

5

—

Unit

ns

ns

ns

ns

µs

µs

µs

µs

µs

µs

µs

ns

ns

PORESET

Input

PORESET

Internal

HRESET

Output (I/O)

SRESET

Output (I/O)

RSTCONF, CNFGS, DSISYNC, DSI64

CHIP_ID[0–3], BM[0–2], SWTE, MODCK[1–2]

1

pins are sampled

Host programs

Reset Configuration

Word

1+2

MODCK[3–5]

SPLL is locked

(no external indication)

2

3

SPLL

Reset configuration write

sequence during this

locking period

5

period.

6

Figure 9. Timing Diagram for a Reset Configuration Write

MSC8122 Quad Digital Signal Processor Data Sheet, Rev. 15

Freescale Semiconductor

21

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