MSC8122 View Datasheet(PDF) - Freescale Semiconductor
Part Name
Description
Manufacturer
MSC8122 Datasheet PDF : 48 Pages
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Electrical Characteristics
Table 15. AC Timing for SIU Outputs
Value for Bus Speed in MHz3
Ref = CLKIN
Ref = CLKOUT
No.
Characteristic
1.1 V 1.2 V 1.2 V
1.2 V
Units
302
31
32a
32b
32c
32d
33a
33b
34
35a
35b
Notes:
100/
133
133
166
100/133
Minimum delay from the 50% level of the REFCLK for all signals
0.9
0.8
0.8
1.0
ns
PSDVAL/TEA/TA max delay from the 50% level of the REFCLK
6.0
4.9
4.9
5.8
ns
rising edge
Address bus max delay from the 50% level of the REFCLK rising
edge
• Multi-master mode (SIUBCR[EBM] = 1)
6.4
5.5
5.5
6.4
ns
• Single-master mode (SIUBCR[EBM] = 0)
5.3
4.2
3.9
5.1
ns
Address attributes: TT[0–1]/TBST/TSZ/GBL max delay from the 50% 6.4
5.1
5.1
6.0
ns
level of the REFCLK rising edge
Address attributes: TT[2–4]/TC max delay from the 50% level of the
6.9
5.7
5.7
6.6
ns
REFCLK rising edge
BADDR max delay from the 50% level of the REFCLK rising edge
5.2
4.2
4.2
5.1
ns
Data bus max delay from the 50% level of the REFCLK rising edge
• Data-pipeline mode
4.8
3.9
3.7
4.8
ns
• Non-pipeline mode
7.1
6.1
6.1
7.0
ns
DP max delay from the 50% level of the REFCLK rising edge
• Data-pipeline mode
6.0
5.3
5.3
6.2
ns
• Non-pipeline mode
7.5
6.5
6.5
7.4
ns
Memory controller signals/ALE/CS[0–4] max delay from the 50%
5.1
4.2
3.9
5.1
ns
level of the REFCLK rising edge
DBG/BG/BR/DBB max delay from the 50% level of the REFCLK
6.0
4.7
4.7
5.6
ns
rising edge
AACK/ABB/TS/CS[5–7] max delay from the 50% level of the
REFCLK rising edge
5.5
4.5
4.5
5.4
ns
1. Values are measured from the 50% level of the REFCLK rising edge to the 50% signal level and assume a 20 pF load except
where otherwise specified.
2. The load for specification 30 is 10 pF. The load for the other specifications in this table is 20 pF. For a 15 pF load, subtract 0.3
ns from the listed value.
3. The maximum bus frequency depends on the mode:
• In 60x-compatible mode connected to another MSC8122 device, the frequency is determined by adding the input and output
longest timing values, which results in the total delay for 20 pF output capacitance. You must also account for other
influences that can affect timing, such as on-board clock skews, on-board noise delays, and so on.
• In single-master mode, the frequency depends on the timing of the devices connected to the MSC8122.
• To achieve maximum performance on the bus in single-master mode, disable the DBB signal by writing a 1 to the
SIUMCR[BDD] bit. See the SIU chapter in the MSC8122 Reference Manual for details.
MSC8122 Quad Digital Signal Processor Data Sheet, Rev. 15
24
Freescale Semiconductor
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