MSC8122 View Datasheet(PDF) - Freescale Semiconductor

Part Name

Description

Manufacturer

MSC8122

Quad Digital Signal Processor

Freescale Semiconductor 

Electrical Characteristics

2.5.5.2 CLKIN to CLKOUT Skew

Table 17 describes the CLKOUT-to-CLKIN skew timing.

No.

20

21

22

23

24

Notes:

Table 16. CLKOUT Skew

Characteristic

Min1

Max1

Units

Rise-to-rise skew

• VDD = 1.1 V

• VDD = 1.2 V

Fall-to-fall skew

• VDD = 1.1 V

• VDD = 1.2 V

CLKOUT phase (1.2 V, 133 MHz)

• Phase high

• Phase low

0.0

0.95

ns

0.0

0.85

ns

–1.5

1.0

ns

–0.8

1.0

ns

2.8

—

ns

2.8

—

ns

CLKOUT phase (1.1 V, 133 MHz)

• Phase high

• Phase low

2.2

—

ns

2.2

—

ns

CLKOUT phase (1.1 V, 100 MHz)

• Phase high

• Phase low

3.3

—

ns

3.3

—

ns

1. A positive number indicates that CLKOUT precedes CLKIN, A negative number indicates that CLKOUT follows CLKIN.

2. Skews are measured in clock mode 29, with a CLKIN:CLKOUT ratio of 1:1. The same skew is valid for all clock modes.

3. CLKOUT skews are measured using a load of 10 pF.

4. CLKOUT skews and phase are not measured for 500/166 Mhz parts because these parts only use CLKIN mode.

For designs that use the CLKOUT synchronization mode, use the skew values listed in Table 16 to adjust the rise-to-fall timing

values specified for CLKIN synchronization. Figure 12 shows the relationship between the CLKOUT and CLKIN timings.

CLKIN

CLKOUT

20

21

Figure 12. CLKOUT and CLKIN Signals.

MSC8122 Quad Digital Signal Processor Data Sheet, Rev. 15

26

Freescale Semiconductor

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