H5TQ2G43CFR-XXC View Datasheet(PDF) - Hynix Semiconductor
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Description
Manufacturer
H5TQ2G43CFR-XXC Datasheet PDF : 33 Pages
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Table 1 -Timings used for IDD and IDDQ Measurement-Loop Patterns
Symbol
tCK
CL
nRCD
nRC
nRAS
nRP
nFAW
1KB page size
2KB page size
nRRD
1KB page size
2KB page size
nRFC -512Mb
nRFC-1 Gb
nRFC- 2 Gb
nRFC- 4 Gb
nRFC- 8 Gb
DDR3-1066
7-7-7
1.875
7
7
27
20
7
20
27
4
6
48
59
86
139
187
DDR3-1333
9-9-9
1.5
9
9
33
24
9
20
30
4
5
60
74
107
174
234
DDR3-1600
11-11-11
1.25
11
11
39
28
11
24
32
5
6
72
88
128
208
280
DDR3-1866
13-13-13
1.071
13
13
45
32
13
26
33
5
6
85
103
150
243
328
DDR3-2133
14-14-14
0.938
14
14
50
36
14
27
38
6
7
97
118
172
279
375
Unit
ns
nCK
nCK
nCK
nCK
nCK
nCK
nCK
nCK
nCK
nCK
nCK
nCK
nCK
nCK
Table 2 -Basic IDD and IDDQ Measurement Conditions
Symbol
Description
Operating One Bank Active-Precharge Current
CKE: High; External clock: On; tCK, nRC, nRAS, CL: see Table 1; BL: 8a); AL: 0; CS: High between ACT
IDD0
and PRE; Command, Address, Bank Address Inputs: partially toggling according to Table 3; Data IO:
MID-LEVEL; DM: stable at 0; Bank Activity: Cycling with one bank active at a time: 0,0,1,1,2,2,... (see
Table 3); Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details:
see Table 3.
Operating One Bank Active-Precharge Current
IDD1
CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, CL: see Table 1; BL: 8a); AL: 0; CS: High between
ACT, RD and PRE; Command, Address; Bank Address Inputs, Data IO: partially toggling according to
Table 4; DM: stable at 0; Bank Activity: Cycling with on bank active at a time: 0,0,1,1,2,2,... (see Table
4); Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see
Table 4.
Rev. 1.0 / Apr. 2013
14
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