H5TQ2G43CFR-XXC View Datasheet(PDF) - Hynix Semiconductor

Part Name

Description

Manufacturer

H5TQ2G43CFR-XXC

2Gb DDR3 SDRAM

Hynix Semiconductor 

Symbol

Active Power-Down Current

Description

IDD3P

CKE: Low; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address,

Bank Address Inputs: stable at 0; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks open;

Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0

Operating Burst Read Current

IDD4R

CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: High between RD; Command,

Address, Bank Address Inputs: partially toggling according to Table 7; Data IO: seamless read data burst

with different data between one burst and the next one according to Table 7; DM: stable at 0; Bank

Activity: all banks open, RD commands cycling through banks: 0,0,1,1,2,2,...(see Table 7); Output Buffer

and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see Table 7.

Operating Burst Write Current

IDD4W

CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: High between WR; Command,

Address, Bank Address Inputs: partially toggling according to Table 8; Data IO: seamless read data burst

with different data between one burst and the next one according to Table 8; DM: stable at 0; Bank

Activity: all banks open, WR commands cycling through banks: 0,0,1,1,2,2,...(see Table 8); Output Buf-

fer and RTT: Enabled in Mode Registersb); ODT Signal: stable at HIGH; Pattern Details: see Table 8.

Burst Refresh Current

IDD5B

CKE: High; External clock: On; tCK, CL, nRFC: see Table 1; BL: 8a); AL: 0; CS: High between REF; Com-

mand, Address, Bank Address Inputs: partially toggling according to Table 9; Data IO: MID_LEVEL; DM:

stable at 0; Bank Activity: REF command every nREF (see Table 9); Output Buffer and RTT: Enabled in

Mode Registersb); ODT Signal: stable at 0; Pattern Details: see Table 9.

Self-Refresh Current: Normal Temperature Range

IDD6

TCASE: 0 - 85 oC; Auto Self-Refresh (ASR): Disabledd);Self-Refresh Temperature Range (SRT): Normale);

CKE: Low; External clock: Off; CK and CK: LOW; CL: see Table 1; BL: 8a); AL: 0; CS, Command, Address,

Bank Address Inputs, Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: Self-Refresh operation; Out-

put Buffer and RTT: Enabled in Mode Registersb); ODT Signal: MID_LEVEL

Self-Refresh Current: Extended Temperature Range (optional)f)

IDD6ET

TCASE: 0 - 95 oC; Auto Self-Refresh (ASR): Disabledd);Self-Refresh Temperature Range (SRT): Extend-

ede); CKE: Low; External clock: Off; CK and CK: LOW; CL: see Table 1; BL: 8a); AL: 0; CS, Command,

Address, Bank Address Inputs, Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: Extended Tempera-

ture Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal:

MID_LEVEL

Rev. 1.0 / Apr. 2013

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