S34ML01G200BFI000(2012) View Datasheet(PDF) - Spansion Inc.
Part Name
Description
Manufacturer
S34ML01G200BFI000 Datasheet PDF : 68 Pages
| |||
Data Sheet (Advance Information)
2. Bus Operation
There are six standard bus operations that control the device: Command Input, Address Input, Data Input,
Data Output, Write Protect, and Standby. (See Table 1.6.)
Typically glitches less than 5 ns on Chip Enable, Write Enable, and Read Enable are ignored by the memory
and do not affect bus operations.
2.1
Command Input
The Command Input bus operation is used to give a command to the memory device. Commands are
accepted with Chip Enable low, Command Latch Enable high, Address Latch Enable low, and Read Enable
high and latched on the rising edge of Write Enable. Moreover, for commands that start a modify operation
(program/erase) the Write Protect pin must be high. See Figure 6.1 on page 38 and Table 5.4 on page 35 for
details of the timing requirements. Command codes are always applied on I/O7:0.
2.2
Address Input
The Address Input bus operation allows the insertion of the memory address. For the S34ML02G2 and
S34ML04G2 devices, five write cycles are needed to input the addresses. For the S34ML01G2, four write
cycles are needed to input the addresses. Addresses are accepted with Chip Enable low, Address Latch
Enable high, Command Latch Enable low, and Read Enable high and latched on the rising edge of Write
Enable. Moreover, for commands that start a modify operation (program/erase) the Write Protect pin must be
high. See Figure 6.2 on page 39 and Table 5.4 on page 35 for details of the timing requirements. Addresses
are always applied on I/O7:0. Refer to Table 1.3 through Table 1.5 on page 15 for more detailed information.
2.3
Data Input
The Data Input bus operation allows the data to be programmed to be sent to the device. The data insertion is
serial and timed by the Write Enable cycles. Data is accepted only with Chip Enable low, Address Latch
Enable low, Command Latch Enable low, Read Enable high, and Write Protect high and latched on the rising
edge of Write Enable. See Figure 6.3 on page 39 and Table 5.4 on page 35 for details of the timing
requirements.
2.4
Data Output
The Data Output bus operation allows data to be read from the memory array and to check the Status
Register content, and the ID data. Data can be serially shifted out by toggling the Read Enable pin with Chip
Enable low, Write Enable high, Address Latch Enable low, and Command Latch Enable low. See Figure 6.4
on page 40 to Figure 6.23 and Table 5.4 on page 35 for details of the timings requirements.
2.5 Write Protect
The Hardware Write Protection is activated when the Write Protect pin is low. In this condition, modify
operations do not start and the content of the memory is not altered. The Write Protect pin is not latched by
Write Enable to ensure the protection even during power up.
2.6 Standby
In Standby, the device is deselected, outputs are disabled, and power consumption is reduced.
16
Spansion® SLC NAND Flash Memory for Embedded
S34ML01G2_04G2_01 August 3, 2012
Share Link: 