S34ML01G200BFI000(2012) View Datasheet(PDF) - Spansion Inc.
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S34ML01G200BFI000 Datasheet PDF : 68 Pages
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Data Sheet (Advance Information)
3.3
3.4
Multiplane Program — S34ML02G2 and S34ML04G2
The S34ML02G2 and S34ML04G2 devices support Multiplane Program, making it possible to program two
pages in parallel, one page per plane.
A Multiplane Program cycle consists of a double serial data loading period in which up to 4224 bytes of data
may be loaded into the data register, followed by a non-volatile programming period where the loaded data is
programmed into the appropriate cell. The serial data loading period begins with inputting the Serial Data
Input command (80h), followed by the five cycle address inputs and serial data for the 1st page. The address
for this page must be in the 1st plane (A18=0). The device supports Random Data Input exactly the same as
in the case of page program operation. The Dummy Page Program Confirm command (11h) stops 1st page
data input and the device becomes busy for a short time (tDBSY). Once it has become ready again, the ‘81h’
command must be issued, followed by 2nd page address (5 cycles) and its serial data input. The address for
this page must be in the 2nd plane (A18=1). Program Confirm command (10h) makes parallel programming
of both pages to start. Figure 6.13 on page 44 describes the sequences.
The user can check operation status by monitoring R/B# pin or reading Status Register commands (70h or
78h), as if it were a normal page program. The Read Status Register command is also available during
Dummy Busy time (tDBSY). In case of failure in any of 1st and 2nd page program, the fail bit of the Status
Register will be set. Refer to Section 3.9 on page 21 for further info.
The number of consecutive partial page programming operations (NOP) within the same page must not
exceed the number indicated in Table 5.7 on page 37. In addition, pages must be programmed sequentially
within a block.
Block Erase
The Block Erase operation is done on a block basis. Block address loading is accomplished in three cycles
(two cycles for S34ML01G2) initiated by an Erase Setup command (60h). Only addresses A18 to A29 (A18 to
A27 for S34ML01G2) are valid while A12 to A17 are ignored.
The Erase Confirm command (D0h) following the block address loading initiates the internal erasing process.
This two-step sequence of setup followed by the execution command ensures that memory contents are not
accidentally erased due to external noise conditions.
At the rising edge of WE# after the erase confirm command input, the internal write controller handles erase
and erase verify. Once the erase process starts, the Read Status Register commands (70h or 78h) may be
issued to read the Status Register.
The system controller can detect the completion of an erase by monitoring the R/B# output, or the Status bit
(I/O6) of the Status Register. Only the Read Status commands (70h or 78h) and Reset command are valid
while erasing is in progress. When the erase operation is completed, the Write Status Bit (I/O0) may be
checked. Figure 6.15 on page 45 details the sequence.
August 3, 2012 S34ML01G2_04G2_01
Spansion® SLC NAND Flash Memory for Embedded
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