S34ML01G200BFI000(2012) View Datasheet(PDF) - Spansion Inc.

Part Name

Description

Manufacturer

S34ML01G200BFI000
(Rev.:2012)

Spansion® SLC NAND Flash Memory for Embedded

Spansion Inc. 

Data Sheet (Advance Information)

3.1

3.2

Page Read

Page Read is initiated by writing 00h and 30h to the command register along with five address cycles

(S34ML02G2 and S34ML04G2). Two types of operations are available: random read and serial page read.

Random read mode is enabled when the page address is changed. All data within the selected page is

transferred to the data registers in less than 25 µs (tR). The system controller may detect the completion of

this data transfer (tR) by analyzing the output of the R/B pin. Once the data in a page is loaded into the data

registers, they may be read out in 25 ns cycle time by sequentially pulsing RE#. The repetitive high to low

transitions of the RE# signal makes the device output the data, starting from the selected column address up

to the last column address.

The device may output random data in a page instead of the sequential data by writing Random Data Output

command. The column address of next data, which is going to be out, may be changed to the address that

follows Random Data Output command. Random Data Output can be performed as many times as needed.

After power up, the device is in read mode, so 00h command cycle is not necessary to start a read operation.

Any operation other than read or Random Data Output causes the device to exit read mode.

See Figure 6.6 on page 41 and Figure 6.12 on page 44 as references.

Page Program

A page program cycle consists of a serial data loading period in which up to a full page of data may be loaded

into the data register, followed by a non-volatile programming period where the loaded data is programmed

into the appropriate cell.

The serial data loading period begins by inputting the Serial Data Input command (80h), followed by the five

cycle address inputs (four cycles for S34ML01G2) and then serial data. The words other than those to be

programmed do not need to be loaded. The device supports Random Data Input within a page. The column

address of next data, which will be entered, may be changed to the address that follows the Random Data

Input command (85h). Random Data Input may be performed as many times as needed.

The Page Program confirm command (10h) initiates the programming process. The internal write state

controller automatically executes the algorithms and controls timings necessary for program and verify,

thereby freeing the system controller for other tasks.

Once the program process starts, the Read Status Register commands (70h or 78h) may be issued to read

the Status Register. The system controller can detect the completion of a program cycle by monitoring the

R/B# output, or the Status bit (I/O6) of the Status Register. Only the Read Status commands (70h or 78h) or

Reset command are valid while programming is in progress. When the Page Program is complete, the Write

Status Bit (I/O0) may be checked. The internal write verify detects only errors for 1’s that are not successfully

programmed to 0’s. The command register remains in Read Status command mode until another valid

command is written to the command register. Figure 6.9 on page 42 and Figure 6.11 on page 43 detail the

sequence.

The device is programmable by page, but it also allows multiple partial page programming of a word or

consecutive bytes up to an entire page in a single page program cycle.

The number of consecutive partial page programming operations (NOP) within the same page must not

exceed the number indicated in Table 5.7 on page 37. In addition, pages must be sequentially programmed

within a block.

18

Spansion® SLC NAND Flash Memory for Embedded

S34ML01G2_04G2_01 August 3, 2012

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