MPC8541CPXAJD(2006) View Datasheet(PDF) - Freescale Semiconductor

Part Name

Description

Manufacturer

MPC8541CPXAJD
(Rev.:2006)

PowerQUICC™ III Integrated Communications Processor Hardware Specifications

Freescale Semiconductor 

DDR SDRAM

Figure 3 shows the DDR SDRAM output timing for address skew with respect to any MCK.

MCK[n]

MCK[n]

tMCK

tAOSKEWmax)

ADDR/CMD

CMD

tAOSKEW(min)

NOOP

ADDR/CMD

CMD

NOOP

Figure 3. Timing Diagram for tAOSKEW Measurement

Figure 4 shows the DDR SDRAM output timing diagram for the source synchronous mode.

MCK[n]

MCK[n]

tMCK

ADDR/CMD

tDDKHAS ,tDDKHCS

tDDKHAX ,tDDKHCX

Write A0

NOOP

tDDKHMP

tDDKHMH

MDQS[n]

MDQ[x]

D0

tDDKHDX

tDDKHDS

tDDKLDS

D1

tDDKLDX

tDDKLME

Figure 4. DDR SDRAM Output Timing Diagram for Source Synchronous Mode

MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specifications, Rev. 4

18

Freescale Semiconductor

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