S25FL127SABMFI003 View Datasheet(PDF) - Cypress Semiconductor
Part Name
Description
Manufacturer
S25FL127SABMFI003 Datasheet PDF : 142 Pages
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S25FL127S
1. Overview
1.1 General Description
The Cypress S25FL127S device is a flash non-volatile memory product using:
MirrorBit technology - that stores two data bits in each memory array transistor
Eclipse architecture - that dramatically improves program and erase performance
65 nm process lithography
This device connects to a host system via a Serial Peripheral Interface (SPI). Traditional SPI single bit serial input and output (Single
I/O or SIO) is supported as well as optional two bit (Dual I/O or DIO) and four bit (Quad I/O or QIO) serial commands. This multiple
width interface is called SPI Multi-I/O or MIO.
The Eclipse architecture features a Page Programming Buffer that allows up to 128 words (256 bytes) or 256 words (512 bytes) to
be programmed in one operation, resulting in faster effective programming and erase than prior generation SPI program or erase
algorithms.
Executing code directly from flash memory is often called Execute-In-Place or XIP. By using FL-S devices at the higher clock rates
supported, with QIO command, the instruction read transfer rate can match or exceed traditional parallel interface, asynchronous,
NOR flash memories while reducing signal count dramatically.
The S25FL127S product offers a high density coupled with the flexibility and fast performance required by a variety of embedded
applications. It is ideal for code shadowing, XIP, and data storage.
Document Number: 001-98282 Rev. *I
Page 4 of 142
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