NT5SV16M8CT View Datasheet(PDF) - Nanya Technology

Part Name

Description

Manufacturer

NT5SV16M8CT

128Mb Synchronous DRAM

Nanya Technology 

NT5SV32M4CT

NT5SV16M8CT

NT5SV8M16CT

128Mb Synchronous DRAM

Write Interrupted by a Read

A Read Command will interrupt a burst write operation on the same clock cycle that the Read Command is registered. The DQs

must be in the high impedance state at least one cycle before the interrupting read data appears on the outputs to avoid data

contention. When the Read Command is registered, any residual data from the burst write cycle will be ignored. Data that is

presented on the DQ pins before the Read Command is initiated will actually be written to the memory.

Minimum Write to Read Interval

(Burst Length = 4, CAS latency = 2, 3)

T0

T1

T2

T3

T4

T5

T6

T7

T8

CK

COMMAND WRITE A

READ B

NOP

NOP

NOP

NOP

NOP

NOP

NOP

CAS latency = 2

tCK2, DQs

DIN A0

CAS latency = 3

tCK3, DQs

DIN A0

DOUT B 0

DOUT B1

DOUT B 2

DOUT B3

DOUT B 0

DOUT B1

DOUT B 2

DOUT B3

: “H” or “L”

Input data for the Write is masked.

Input data must be removed from the DQs at least one clock

cycle before the Read data appears on the outputs to avoid

data contention.

REV 1.0

May, 2001

15

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NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

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