NT5SV16M8CT View Datasheet(PDF) - Nanya Technology
Part Name
Description
Manufacturer
NT5SV16M8CT Datasheet PDF : 66 Pages
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NT5SV32M4CT
NT5SV16M8CT
NT5SV8M16CT
128Mb Synchronous DRAM
If A10 is high when a Write Command is issued, the Write with Auto-Precharge function is initiated. The bank undergoing auto-
precharge cannot be reactivated until tDAL, Data-in to Active delay, is satisfied.
Burst Write with Auto-Precharge
(Burst Length = 2, CAS Latency = 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK
COMMAND
WRITE A
Auto-Precharge
NOP
CAS latency = 2
tCK2, DQs
DIN A 0
DIN A1
CAS latency = 3
tCK3, DQs
DIN A0
DIN A1
NOP
NOP
tDAL‡
tDAL‡
NOP
*
NOP
NOP
NOP
NOP
*
*Bank can be reactivated at completion of tDAL.
‡ tDAL is a function of clock cycle time and speed sort.
See the Clock Frequency and Latency table.
Similar to the Read Command, a Write Command with auto-precharge can not be interrupted by a command to the same bank.
It can be interrupted by a Read or Write Command to a different bank, however. The interrupting command will terminate the
write. The bank undergoing auto-precharge can not be reactivated until tDAL is satisfied.
Burst Write with Auto-Precharge Interrupted by Write
(Burst Length = 4, CAS Latency = 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK
COMMAND WRITE A
Auto-Precharge
CAS latency = 3
tCK3, DQs
DIN A 0
NOP
DIN A 1
WRITE B
NOP
tDAL ‡
DIN B 0
DIN B 1
NOP
DIN B2
NOP
*
DIN B3
NOP
NOP
NOP
*Bank can be reactivated at completion of tDAL.
‡ tDAL is a function of clock cycle time and speed sort.
See the Clock Frequency and Latency table.
REV 1.0
May, 2001
20
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NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
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