NT5SV16M8CT View Datasheet(PDF) - Nanya Technology
Part Name
Description
Manufacturer
NT5SV16M8CT Datasheet PDF : 66 Pages
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NT5SV32M4CT
NT5SV16M8CT
NT5SV8M16CT
128Mb Synchronous DRAM
Although a Read Command with auto-precharge can not be interrupted by a command to the same bank, it can be interrupted
by a Read or Write Command to a different bank. If the command is issued before auto-precharge begins then the precharge
function will begin with the new command. The bank being auto-precharged may be reactivated after the delay tRP.
Burst Read with Auto-Precharge Interrupted by Read
(Burst Length = 4, CAS Latency = 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK
COMMAND
READ A
Auto-Precharge
NOP
CAS latency = 2
tCK2, DQs
CAS latency = 3
tCK3, DQs
READ B
NOP
DOUT A 0
tRP‡
DOUT A1
NOP
*
DOUT B 0
tRP‡
DOUT A0
DOUT A 1
NOP
DOUT B 1
*
DOUT B 0
NOP
DOUT B2
DOUT B1
NOP
DOUT B 3
DOUT B2
NOP
DOUT B 3
*Bank can be reactivated at completion of tRP.
‡ tRP is a function of clock cycle time and speed sort.
See the Clock Frequency and Latency table.
If interrupting a Read Command with auto-precharge with a Write Command, DQM must be used to avoid DQ contention.
Burst Read with Auto-Precharge Interrupted by Write
(Burst Length = 8, CAS Latency = 2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK
COMMAND
READ A
Auto-Precharge
NOP
CAS latency = 2
tCK2, DQs
NOP
NOP
DOUT A 0
WRITE B
NOP
DIN B0
tRP‡
D IN B 1
NOP
*
DIN B2
NOP
DIN B 3
NOP
DIN B4
DQM
*Bank can be reactivated at completion of tRP.
‡ tRP is a function of clock cycle time and speed sort. .
See the Clock Frequency and Latency table .
REV 1.0
May, 2001
19
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NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
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