S25FL016A View Datasheet(PDF) - Spansion Inc.
Part Name
Description
Manufacturer
S25FL016A
Spansion Inc.
S25FL016A Datasheet PDF : 36 Pages
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Data Sheet
CS#
Mode 3
SCK Mode 0
SI
Figure 9.8 Page Program (PP) Command Sequence
0 1 2 3 4 5 6 7 8 9 10
28 29 30 31 32 33 34 35 36 37 38 39
Command
24-Bit Address
Data Byte 1
23 22 21
32 1 076 54 3 2 10
MSB
MSB
CS#
SCK
SI
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
Data Byte 2
Data Byte 3
765 4 32 107 6 5 4 32 10
MSB
MSB
Data Byte 256
765 43210
MSB
9.9
Sector Erase (SE)
The Sector Erase (SE) command sets all bits at all addresses within a specified sector to a logic 1. A WREN
command is required prior to writing the PP command.
The host system must drive CS# low, and then write the SE command plus three address bytes on SI. Any
address within the sector (see Table 7.1 on page 13) is a valid address for the SE command. CS# must be
driven low for the entire duration of the SE sequence. The command sequence is shown in Figure 9.9 and
Table 9.4 on page 25.
The host system must drive CS# high after the device has latched the 8th bit of the SE command, otherwise
the device does not execute the command. The SE operation begins as soon as CS# is driven high. The
device internally controls the timing of the operation, which requires a period of tSE. The Status Register may
be read to check the value of the Write In Progress (WIP) bit while the SE operation is in progress. The WIP
bit is 1 during the SE operation, and is 0 when the operation is completed. The device internally resets the
Write Enable Latch to 0 before the operation completes (the exact timing is not specified).
The device does not execute an SE command that specifies a sector that is protected by the Block Protect
bits (BP2:BP0) (see Table 7.1 on page 13).
CS#
Mode 3
SCK
Mode 0
SI
SO Hi-Z
Figure 9.9 Sector Erase (SE) Command Sequence
0 1 2 3 4 5 6 7 8 9 10 28 29 30 31
Command
24-bit Address
23 22 21
MSB
3 21 0
22
S25FL016A
S25FL016A_00_C3 January 7, 2008
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