S25FL016A View Datasheet(PDF) - Spansion Inc.

Part Name

Description

Manufacturer

S25FL016A

16 Megabit CMOS 3.0 Volt Flash Memory with 50-MHz SPI (Serial Peripheral Interface) Bus

Spansion Inc. 

Data Sheet

9.10

Bulk Erase (BE)

The Bulk Erase (BE) command sets all the bits within the entire memory array to logic 1s. A WREN command

is required prior to writing the PP command.

The host system must drive CS# low, and then write the BE command on SI. CS# must be driven low for the

entire duration of the BE sequence. The command sequence is shown in Figure 9.10 and Table 9.4

on page 25.

The host system must drive CS# high after the device has latched the 8th bit of the CE command, otherwise

the device does not execute the command. The BE operation begins as soon as CS# is driven high. The

device internally controls the timing of the operation, which requires a period of tBE. The Status Register may

be read to check the value of the Write In Progress (WIP) bit while the BE operation is in progress. The WIP

bit is 1 during the BE operation, and is 0 when the operation is completed. The device internally resets the

Write Enable Latch to 0 before the operation completes (the exact timing is not specified).

The device only executes a BE command if all Block Protect bits (BP2:BP0) are 0 (see Table 7.1

on page 13). Otherwise, the device ignores the command.

Figure 9.10 Bulk Erase (BE) Command Sequence

CS#

Mode 3

SCK

Mode 0

0 1 23 4 5 6 7

Command

SI

SO Hi-Z

9.11

Deep Power Down (DP)

The Deep Power Down (DP) command provides the lowest power consumption mode of the device. It is

intended for periods when the device is not in active use, and ignores all commands except for the Release

from Deep Power Down (RES) command. The DP mode therefore provides the maximum data protection

against unintended write operations. The standard standby mode, which the device goes into automatically

when CS# is high (and all operations in progress are complete), should generally be used for the lowest

power consumption when the quickest return to device activity is required.

The host system must drive CS# low, and then write the DP command on SI. CS# must be driven low for the

entire duration of the DP sequence. The command sequence is shown in Figure 9.11 and Table 9.4

on page 25.

The host system must drive CS# high after the device has latched the 8th bit of the DP command, otherwise

the device does not execute the command. After a delay of tDP, the device enters the DP mode and current

reduces from ISB to IDP (see Table 14.1 on page 28).

Once the device has entered the DP mode, all commands are ignored except the RES command (which

releases the device from the DP mode). The RES command also provides the Electronic Signature of the

device to be output on SO, if desired (see Section 9.12 and 9.12.1).

DP mode automatically terminates when power is removed, and the device always powers up in the standard

standby mode. The device rejects any DP command issued while it is executing a program, erase, or Write

Status Register operation, and continues the operation uninterrupted.

January 7, 2008 S25FL016A_00_C3

S25FL016A

23

Share Link: