S25FL016A View Datasheet(PDF) - Spansion Inc.
Part Name
Description
Manufacturer
S25FL016A
Spansion Inc.
S25FL016A Datasheet PDF : 36 Pages
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Data Sheet
10. Power-up and Power-down
During power-up and power-down, certain conditions must be observed. CS# must follow the voltage applied
on VCC, and must not be driven low to select the device until VCC reaches the allowable values as follows
(see Figure 10.1 and Table 10.1 on page 26):
At power-up, VCC (min) plus a period of tPU
At power-down, VSS
A pull-up resistor on Chip Select (CS#) typically meets proper power-up and power-down requirements.
No Write Status Register, program, or erase command should be sent to the device until VCC rises to the VCC
min, plus a delay of tPU. At power-up, the device is in standby mode (not Deep Power Down mode) and the
WEL bit is reset (0).
Each device in the host system should have the VCC rail decoupled by a suitable capacitor close to the
package pins (this capacitor is generally of the order of 0.1 µF), as a precaution to stabilizing the VCC feed.
When VCC drops from the operating voltage to below the minimum VCC threshold at power-down, all
operations are disabled and the device does not respond to any commands. Note that data corruption may
result if a power-down occurs while a Write Register, program, or erase operation is in progress.
Figure 10.1 Power-Up Timing Diagram
Vcc
Vcc(max)
Vcc(min)
t PU
Full Device Access
Time
Symbol
VCC(min)
tPU
Table 10.1 Power-Up Timing Characteristics
Parameter
VCC (minimum)
VCC (min) to device operation
Min
Max
Unit
2.7
V
10
ms
11. Initial Delivery State
The device is delivered with all bits set to 1 (each byte contains FFh) upon initial factory shipment. The Status
Register contains 00h (all Status Register bits are 0).
26
S25FL016A
S25FL016A_00_C3 January 7, 2008
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