SPHE8200A View Datasheet(PDF) - Unspecified

Part Name

Description

Manufacturer

SPHE8200A

DVD Single Chip MPEG AV Processor

Unspecified 

Preliminary

SPHE8200A

Signal

IR_IN/TDM_DR

Pin

State

Description

153

I/O

GPIO (for IR) or TDM data receive

tial GY VFD_CLK/TDM_D

154

X

nfidenNOLOINC VFD_STB/TDM_FS

155

o H E X

nplus ICC TECNDISLY VFD_DATA/TDM_C

156

A LK

FoSruS&UNMNERCUHSE ON UA0_RX/GPIO

175

Priority selection

sft_cfg4[14:13]=2’b10

(other)

Function

TDM_DR

GPIO[53] (default)

I/O

GPIO (for VFD clock) or TDM data transmit

This pin must be pull-high to 3.3v.

Priority selection

sft_cfg4[14:13]=2’b10

(other)

Function

TDM_DX

GPIO[54] (default)

I/O

GPIO (for VFD strobe) or TDM frame sync

This pin must be pull-high to 3.3v.

Priority selection

sft_cfg4[14:13]=2’b10

(other)

Function

TDM_FSXR

GPIO[55] (default)

I/O

GPIO (for VFD data) or TDM clock

This pin must be pull-high to 3.3v.

Priority selection

sft_cfg4[14:13]=2’b10

(other)

Function

TDM_CLK

GPIO[56] (default)

I/O

UART #0 data receive or GPIO

Priority selection

sft_cfg2[4:2]=3’b101

Function

UART0_RX (default)

(other)

GPIO[62]

UA0_TX/GPIO

176

I/O

UART #0 data transmit or GPIO

Priority selection

sft_cfg2[4:2]=3’b101

(other)

Function

UART0_TX (default)

GPIO[63]

AIN/AIN_L

AI_BCK

Audio ADC pins (4)

157

A

ADC input (left channel, with OP)

(bonding option) Digital audio input interface bit clock

© Sunplus Technology Co., Ltd.

15

Proprietary & Confidential

OCT. 07, 2003

Preliminary Version: 0.2

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