SPHE8200A View Datasheet(PDF) - Unspecified

Part Name

Description

Manufacturer

SPHE8200A

DVD Single Chip MPEG AV Processor

Unspecified 

Preliminary

SPHE8200A

5.FUNCTIONAL DESCRIPTIONS

SPHE8200 is a highly integrated system-on-chip design. It

includes DVD/CD servo controller, RISC processor, MPEG1/2

video decoder, programmable audio decoder, programmable

CLKI

27MHz

PLLa

147.456MHz

135.4752MHz

CLK_PLLA AUDCLK_GEN

XCK

ADCLK

IECCLK

peripheral controller, audio ADC and multi-format TV-encoder on a

single chip.

tial Y 5.1. PLL and ClockGen

G SPHE8200 contains two PLLs to generate system clock (PLLv)

n O and audio reference clocks (PLLa). Both the PLLs reference a

single external 27MHz clock or crystal to generate all the required

e L clocks.

fid O C System clock is then derived from division of the PLLv output.

on HN E IN CLKI

27MHz

PLLv

Fractional multiples

of CLKI

CLK_PLL SYSCLK_GEN SYSCLK

/2, /4 ~ /65536

s C EC IS OptionVideoClockIn

VIDCLK_GEN VIDCLK

nplu IC T AND LY Some pre-defined PLLv/SYSCLK frequencies are listed below:

N SYSCLK Frequency

PLLV Frequency

u N H O 101.25MHz

405MHz

S N C 108MHz

216MHz

U R E 114.75MHz

459MHz

121.5MHz

486MHz

S E S 128.25MHz

256.5MHz

r U 135MHz

270MHz

o M 141.75MHz

283.5MHz

148.5MHz

297MHz

F & 155.25MHz

310.5MHz

5.2. Power Control

SPHE8200 provides various levels of power-control mechanism in

order to achieve minimum power consumption.

Automatic power-save:

Most hardware modules are automatically power-saved when

not operating.

Module-level stop-operation:

SPHE8200 provides a function to turn off specific module from

operating. Without explicit wake-up, the hardware module will

remain static and consume very little power.

System-level doze:

For maximum power-saving, firmware could fine-tune system

performance according to system task.

5.3. Embedded 32-bit RISC Controller

SPHE8200 includes a powerful 32-bit RISC processor. This RISC

processor is utilized to manage decoding tasks as well as UI tasks.

It can access to all the memory and devices, cooperate between

processor systems. Audio decoder and I/O processor handshake

with RISC processor through the mailbox registers.

RISC

subsyste

mailbo

(16x16

mailbo

Audio

decoder

I/O

(16x8)

processo

162MHz

324MHz

168.75MHz

337.5MHz

175.5MHz

351MHz

Figure 5-1: Communication between processors

182.25MHz

189MHz

364.5MHz

378MHz

The RISC processor is equipped with instruction and data caches.

These caches can accelerate accesses to the SDRAM or ROM

PLLa supports two center frequencies (for 48kHz family or

cacheable regions.

44.1kHz family) and generates required audio clocks from the

audio system clock.

© Sunplus Technology Co., Ltd.

18

Proprietary & Confidential

OCT. 07, 2003

Preliminary Version: 0.2

Share Link: