SPHE8200A View Datasheet(PDF) - Unspecified
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SPHE8200A Datasheet PDF : 40 Pages
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Preliminary
SPHE8200A
5.5. ROM/Flash/SRAM controller
5.7. Peripheral Control Interface
The SPHE8200 provides flexible connections to external ROM,
RISC firmware controls on-chip devices (such as video decoder,
Flash or SRAM (RFS). It can support up to 4 external RFS devices
audio decoder..) by a dedicated peripheral control interface.
by using different chip-selects (R_CS_B[3:0]). The firmware can
Firmware controls the hardware behavior by writing to specific
configure RFS memory anchor registers and map these devices
into locations of memory space. For each memory space it can
l Y be in flash mode or in ISA mode. In FLASH mode the access
tia timing is decided by wait-state setting, while in ISA mode the
G controller will reference external IO_CHRDY input.
en LO Prefetch
buffer
nfid NO INC Processor
local bus
Address Address
translator sequencer
External
ROM
interface
o H E Wait state
C C generation
s E IS Figure 5-4: ROM/FLASH/SRAM controller
lu T D Y ROM/Flashmode
np IC N L CSB
wait
A N ADDR[]
Address (read)
u N H OEB
oe_setup
oe_hold
O WEB
S UN RC E DATA[]
Data (read)
data is sampled at this point
wait
Address (write)
we_setup
we_hold
DATA (for write)
S E S Figure 5-5: ROM/FLASH/SRAM mode timing
hardware registers with this interface.
5.8. CSS/CPPM support
SPHE8200 have built-in CSS and CPPM hardware support. For
CSS the system supports accelerated DMA. For CPPM the
system supports C2_D/C2_E and C2_DCBC functions.
5.9. MPEG Video Decoder
The system incorporates a powerful MPEG video decoding
datapath and provides real-time video decoding of MPEGI/II
bitstream. The bitstream can come from Servo hardware, ATAPI,
TDM or UART. This enables various applications to be built over
SPHE8200 such as real-time broadcasting over Ethernet.
The video decoder is a hardwired MPEG1/2 datapath. The system
architecture is as in the figure. RISC subsystem is in charge of
de-multiplexing the data and buffering formatted video data into
video bitstream buffer resided in external SDRAM. Upon correct
timing video decoder will decode the bitstream and write back
reconstructed video frame for playback.
RISC
subsystem control bus
Video
decoder
or M U ISAMODE
F & CSB
wait
iochrdy_hold
wait
iochrdy_hold
memory bus
ADDR[]
Address (read)
Address (write)
OEB
WEB
oe_setup
oe_hold
we_setup
we_hold
External
SDRAM
IO_RDY
DATA[]
Data (read)
data is sampled at this point
DATA (for write)
Figure 5-7: Interface between RISC and Video decoder
Figure 5-6: ISA mode timing
5.6. RISC Memory Interface
RISC memory interface provides a fast-path between processor
local bus and system memory bus. Local bus transactions are
mapped to system memory bus tasks.
Advanced video decoding and display control mechanism is
included to prevent tearing effect.
© Sunplus Technology Co., Ltd.
20
Proprietary & Confidential
OCT. 07, 2003
Preliminary Version: 0.2
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