SPHE8200A View Datasheet(PDF) - Unspecified

Part Name

Description

Manufacturer

SPHE8200A

DVD Single Chip MPEG AV Processor

Unspecified 

Preliminary

SPHE8200A

I-CACHE

Peripheral

Control bus

Other

modules

edge-trigger and level-sensitive mode.

Watchdog:

RISC32

Watchdog keeps monitoring RISC behavior and whenever

core

BIU

D-CACHE

l Y D-RAM

tia DMA

ROM/Flash

interface

System Bus

Interface

ROM

FLASH

SRAM

DRAM

n OG Figure 5-2: RISC subsystem

Table: RISC processor configuration

e L Specification

fid O C I-Cache

8kbyte (2-way set associated)

n N IN D-Cache

4kbyte (direct-mapped)

D-RAM/DMA

1kbyte scratch buffer

o H E The RISC sub-system is able to bootstrap from multiple sources.

s C EC IS In typical application the RISC processor boots from external ROM

device #1. Besides that, it also supports standalone booting

without pre-loaded firmware.

nplu IC T ND LY 5.4.RISC interface

A RISC controllers interface to system via various interface control

N modules. These interface modules are mapped to the processor

u N H memory map and firmware could operate on them via typical

S O memory accesses. These controllers include:

N C ROM/FLASH/SRAM (RFS) controller

U R E RISC Memory Interface controller (SDRAM)

S E S Peripheral control interface

r U The RISC memory mapping of these controllers is shown in

o M following table:

F & Table: RISC memory mapping

firmware is in a deadlock, it can try to reset the system and

keep the application functioning continuously.

Timers

There are 4-channel timers and 2 cascade counters for timed

tasks. During A/V decoding, counters are utilized to

synchronize audio and video.

RISC

subsystem

to RISC interrupt

Device

interrupt

controller

RISC

monitor

monitor

interrupt

Watchdog

watchdog

reset

Timers

timer

interrupt

Figure 5-3: RISC dedicated hardware

Table: Device interrupt controller sources

Symbol

Description

INT_WDOG

Watchdog interrupt (if reset disabled)

INT_HSYNC

Interrupt when horizontal resync

INT_VSYNC

Interrupt when enter vertical resync

INT_FLD_ACT Interrupt when enter active region

INT_FLD_SYNC Interrupt when leave active region

INT_HOST

Host device interrupt

INT_TIMER0

Timer 0 interrupt

INT_TIMER1

Timer 1 interrupt

INT_TIMER2A Timer 2 scale interrupt

INT_TIMER2B Timer 2 count interrupt

Memory range

Description

INT_TIMER3A Timer 3 scale interrupt

8000_0000-87ff_ffff SDRAM (cached)

INT_TIMER3B Timer 3 count interrupt

a000_0000-a7ff_ffff SDRAM (uncached)

INT_TIMERW

Watchdog timer interrupt

8800_0000-8fbf_ffff ROM/FLASH/SRAM (cached)

INT_UART0

UART0 interrupt

a800_0000-afbf_ffff

affe_8000-affe_ffff

afff_0000-afff_03ff

ROM/FLASH/SRAM (uncached)

Peripheral control registers

DMA buffer

INT_UART1

INT_VDP0

INT_DSP

UART1 interrupt

Video decoder interrupt

DSP interrupt

INT_EXT0

External interrupt #0

In additional to that, SPHE8200 includes dedicated RISC

INT_EXT1

External interrupt #1

peripherals to assist the system tasks:

INT_EXT2

External interrupt #2

Device interrupt controller:

INT_EXT3

External interrupt #3

Device interrupt controller takes care of interrupt sources from

INT_IOP

IOP interrupt

on-chip devices and off chip sources. For each interrupt source

the firmware is able to configure the interrupt behavior between

INT_AUD

Audio hardware interrupt

© Sunplus Technology Co., Ltd.

19

Proprietary & Confidential

OCT. 07, 2003

Preliminary Version: 0.2

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