56F8357 View Datasheet(PDF) - Motorola => Freescale
Part Name
Description
Manufacturer
56F8357 Datasheet PDF : 160 Pages
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Freescale Semiconductor, Inc.
56F8357 Signal Pins
Table 2-2 56F8357 Signal and Package Information for the 160-Pin LQFP
Signal Name Pin No. Type
State
During
Reset
Signal Description
VSSA_ADC
115
Supply
ADC Analog Ground — This pin supplies an analog
ground to the ADC modules.
OCR_DIS
91
Input
Input
On-Chip Regulator Disable —
Tie this pin to VSS to enable the on-chip regulator
Tie this pin to VDD to disable the on-chip regulator
This pin is intended to be a static DC signal from
power-up to shut down. Do not try to toggle this pin
for power savings during operation.
VCAP1*
VCAP2*
VCAP3*
VCAP4*
62
Supply
Supply
VCAP1 - 4 — When OCR_DIS is tied to VSS (regulator
enabled), connect each pin to a 2.2µF or greater bypass
144
capacitor in order to bypass the core logic voltage
regulator, required for proper chip operation. When
95
OCR_DIS is tied to VDD (regulator disabled), these pins
become VDD_CORE and should be connected to a
15
regulated 2.5V power supply.
Note: This bypass is required even if the chip is
powered with an external supply.
VPP1
VPP2
141
Input
2
Input
VPP1 - 2 — These pins should be left unconnected as an
open circuit for normal functionality.
CLKMODE
99
Input
Input
Clock Input Mode Selection — This input determines the
function of the XTAL and EXTAL pins.
1 = External clock input on XTAL is used to directly drive
the input clock of the chip. The EXTAL pin should be
grounded.
0 = A crystal or ceramic resonator should be connected
between XTAL and EXTAL.
EXTAL
94
Input
Input
External Crystal Oscillator Input — This input can be
connected to an 8MHz external crystal. Tie this pin low if
XTAL is driven by an external clock source.
XTAL
93
Input/ Chip-driven Crystal Oscillator Output — This output connects the
Output
internal crystal oscillator output to an external crystal.
If an external clock is used, XTAL must be used as the
input and EXTAL connected to GND.
The input clock can be selected to provide the clock
directly to the core. This input clock can also be selected
as the input clock for the on-chip PLL.
* When the on-chip regulator is disabled, these four pins become 2.5V VDD_CORE.
56F8357 Technical Data
15
Preliminary
For More Information On This Product,
Go to: www.freescale.com
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