56F8357 View Datasheet(PDF) - Motorola => Freescale

Part Name

Description

Manufacturer

56F8357

16-bit Digital Signal Processor

Motorola => Freescale 

Freescale Semiconductor, Inc.

Table 2-2 56F8357 Signal and Package Information for the 160-Pin LQFP

Signal Name Pin No. Type

State

During

Reset

Signal Description

WR

PS

(CS0)

(GPIOD8)

DS

(CS1)

(GPIOD9)

51

Output Tri-stated Write Enable — WR is asserted during external memory

write cycles. When WR is asserted low, pins D0 - D15

become outputs and the device puts data on the bus.

When WR is deasserted high, the external data is latched

inside the external device. When WR is asserted, it

qualifies the A0 - A23, PS, DS, and CSn pins. WR can be

connected directly to the WE pin of a static RAM.

Depending upon the state of the DRV bit in the EMI bus

control register (BCR), WR is tri-stated when the external bus

is inactive.

To deactivate the internal pull-up resistor, set the CTRL bit

in the SIM_PUDR register.

53

Output Tri-stated Program Memory Select — This signal is actually CS0 in

the EMI, which is programmed at reset for compatibility

with the 56F80x PS signal. PS is asserted low for external

program memory access.

Depending upon the state of the DRV bit in the EMI bus

control register (BCR), CS0 is tri-stated when the external

bus is inactive.

Input/

Output

Input

Port D GPIO — This GPIO pin can be individually

programmed as an input or output pin.

CS0 resets to provide the PS function as defined on the

56F80x devices.

To deactivate the internal pull-up resistor, clear bit 8 in the

GPIOD_PUR register.

54

Output

Tri-stated Data Memory Select — This signal is actually CS1 in the

EMI, which is programmed at reset for compatibility with

the 56F80x DS signal. DS is asserted low for external data

memory access.

Depending upon the state of the DRV bit in the EMI bus

control register (BCR), CS1 is tri-stated when the external

bus is inactive.

Input/

Output

Input

Port D GPIO — This GPIO pin can be individually

programmed as an input or output pin.

To deactivate the internal pull-up resistor, clear bit 9 in the

GPIOD_PUR register.

20

56F8357 Technical Data

For More Information On This Product,

Preliminary

Go to: www.freescale.com

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