LS7166 View Datasheet(PDF) - LSI Corporation

Part Name

Description

Manufacturer

LS7166

24-BIT QUADRATURE COUNTER

LSI Corporation  

TABLE 1 - Register Addressing Modes

D7 D6 C/D RD WR CS

XX X X X 1

001 1

0

COMMENT

Disable Chip for READ/WRITE

Write to Master Control Register (MCR)

01 11

0

Write to input control register (ICR)

10 11

0

Write to output/counter control register (OCCR)

11 11

XX01

0

Write to quadrature register (QR)

0

Write to preset register (PR) and increment register

address counter.

XX0

10

Read output latch (OL) and increment register

address counter

XX1

10

Read output status register (OSR).

X = Don't Care

OSR (Output Status Register). Indicates CNTR status: Accessed by: READ when C/D = 1, CS = 0.

Bit # 7 6 5 4 3 2 1 0

U U U 0/1 0/1 0/1 0/1 0/1

U = Undefined

BWT. Borrow Toggle Flip-Flop. Toggles everytime CNTR underflows

generating a borrow.

CYT. Carry Toggle Flip-Flop. Toggles everytime CNTR overflows

generating a carry.

COMPT. Compare Toggle Flip-Flop. Toggles everytime CNTR equals PR

SIGN. Sign bit. Reset ( = 0) when CNTR underflows

Set ( = 1) when CNTR overflows

UP/DOWN. Count direction indicatior in quadrature mode.

Reset ( = 0) when counting down

Set ( = 1) when counting up

(Forced to 1 in non-quadrature mode)

OL(Output latch). The OL is the output port for the CNTR. The 24 bit CNTR Value at any instant can be accessed

by performing a CNTR to OL transfer and then reading the OL in 3 READ cycle sequence of Byte 0 (OL0), Byte 1 (OL1)

and Byte 2 (OL2). The address pointer for OL0/OL1/OL2 is automatically incremented with each READ cycle.

Accessed by: READ when C/D = 0, CS = 0.

Bit #

7

07

07

0

OL2

(BYTE 2)

OL1

(BYTE 1)

OL0

(BYTE 0)

Standard Sequence for Loading and Reading OL:

3

MCR

; Reset OL address pointer and Transfer CNTR to OL

READ OL

; Read Byte 0 and increment address

READ OL

; Read Byte 1 and increment address

READ OL

; Read Byte 2 and increment address

7166-110103-3

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