LS7166 View Datasheet(PDF) - LSI Corporation
Part Name
Description
Manufacturer
LS7166 Datasheet PDF : 15 Pages
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TRANSIENT CHARACTERISTICS (See Timing Diagrams in Fig. 2 thru Fig. 7,
VDD = 3V to 5.5V, TA = 0˚ to 85˚C, unless otherwise specified)
Parameter
Clock A/B "Low”
Clock A/B "High"
Clock A/B Frequency
(See NOTE 1)
Clock UP/DN Reversal
Delay
LCTR Positive edge to
the next A/B positive or
negative edge delay
Clock A/B to
CY/BW/COMP "low"
propagation delay
Clock A/B to
CY/BW/COMP "high"
propagation delay
LCTR and LLTC pulse
width
Clock A/B to CYT, BWT
and COMPT "high"
propagation delay
Clock A/B to CYT, BWT
and COMPT "low"
progagation delay
WR pulse width
RD to data out delay
(CL=20pF)
CS, RD Terminate to
Data-Bus Tri-State
Data-Bus set-up
time for WR
Data-Bus hold time for WR
Symbol
TCL
TCH
fc
TUDD
TLC
TCBL
TCBH
TLCW
TTFH
TTFL
TWR
TR
TRT
TDS
TDH
Min.Value
18
22
0
100
100
-
-
60
-
-
60
-
-
30
30
Max.Value
No Limit
No Limit
25
-
-
65
85
-
100
100
-
110
30
-
-
CS set-up time for RD
CS hold time for RD
Back to Back RD delay
RD to WR delay
C/D set-up time for RD
C/D hold time for RD
C/D set-up time for WR
C/D hold time for WR
CS set-up time for WR
CS hold time for WR
Back to Back WR delay
WR to RD delay
TSRS
TSRH
TRR
-
TCRS
TCRH
TCWS
TCWH
TSWS
TSWH
Tww
-
0
-
0
-
60
-
60
-
0
30
30
-
30
-
60
-
0
-
60
-
60
-
Quadrature Mode:
Clock A/B Validation delay
(See NOTE 1)
A and B phase delay
Clock A/B frequency
CY, BW, COMP pulse width
TCQV
TPH
fCQ
TCBW
-
160
208
-
-
1.2
85
200
NOTE 1: In quadrature mode A/B inputs are filtered and required to be stable
for at least TCQV length to be valid.
7166-011705-6
Unit
ns
ns
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
ns
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