AHA4011C View Datasheet(PDF) - Unspecified

Part Name

Description

Manufacturer

AHA4011C

10 MBytes/sec Reed-Solomon Error Correction Device

Unspecified 

Advanced Hardware Architectures, Inc.

In pass-through operation, data flows through

the device similar to the encode and decode

operations. During initialization the device is

programmed as shown above. Check Bytes are

programmed in the range of 0x02 to 0x14.5. The

Block length here is the sum of Message Bytes and

Check Bytes like encode and decode modes of

operation even though the device passes through the

block of data unchanged.

1) Following initialization, the system clocks

the codeword into the Input Buffer.

2) The codeword is processed by the ECC

module and passed on to the Output Buffer

without correction.

3) The uncorrected codeword is available at

the output port. State of the RDYON

determines the availability of valid data.

The ERASE input is ignored during the

Input phase and ERR and CRTN outputs

are not valid.

Caveat: The device has no provisions for indicating

the start and/or end of message or check bytes. It is

the system designers responsibility to keep track of

message and check bytes transitions, if required.

2.8 BUFFERS

The Input Port contains a single-ported 367x9

buffer. The Output Port contains a single-ported

256x9 buffer. These buffers store input and output

data during the correction process and help maintain

the desired system data rate. A Reset operation as

described in the Initialization Sequence section

clears the buffers.

The use of internal buffers is restricted per the

rules defined in Section 2.9 Data Rates and

Latencies. These rules define the limitations of

using the buffers to temporarily store more than one

block. It is highly recommended that the system

designer clearly understand these rules prior to

designing the system.

The Input Buffer receives input data on the DI

bus when the ECC module is in the calculation or in

data-out phases at the desired system rate. The

ability of the Input Buffer to accept data is indicated

by RDYIN.

The Output Buffer accepts corrected data from

the ECC during the data-out phase. RDYON is

asserted low when the Output Buffer is able to

output data.

Data flow through the device may occur in burst

or continuous rates. The number of clocks per byte

used to input or output determines burst or

continuous operating conditions. Figure 4 shows the

two operations.

Burst operation permits data to be clocked in

and out of the device at the maximum rate, i.e., 1

clock per byte. In burst operation, consecutive data

blocks are clocked into the device following a

processing latency period. Data is input into the

Input Buffer and processed through the ECC core.

After a processing latency period the entire block of

data is transferred to the Output Buffer. While the

Output Buffer is being emptied, the Input Buffer is

simultaneously filled with the following block at the

maximum rate. Input and output rates are controlled

by the clock speed and clocks/byte.

Continuous operation requires a minimum of 4

clocks/byte depending upon the block size.

Maximum data transfer rates for continuous rate

vary accordingly. Blocks may be processed

continuously through the device. If the chip is

operated with continuous data streams, the RDYIN

and RDYON pins will always be active (after the

initial latency). Therefore, they need not be used.

Caveat: System designer should be aware that data

is put into the Output Buffer in reverse order.

Therefore, RDYON may become inactive between

blocks in forward order if data is output faster than

Output Buffer is filled.

2.9 DATA RATES AND LATENCIES

This section describes data rates and processing

latencies for burst and continuous operations.

Processing latencies are the same in encode, decode

or pass-through operations. The number of clocks

used to clock in and out of the device determines the

operation. The input and output rates need not be the

same. No registers are required to program the

device for either operation.

Continuous block flow is achieved by using the

appropriate number of clocks per byte and block

length. Alternatively, data flow into and out of the

device is controlled using control signals, DSIN and

DSON.

Page 8 of 24

PS4011C-0200

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