AHA4011C View Datasheet(PDF) - Unspecified
Part Name
Description
Manufacturer
AHA4011C Datasheet PDF : 28 Pages
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Advanced Hardware Architectures, Inc.
3.4 DATA OUTPUT
The DO pins are driven from a register clocked on the rising edge of CLK.
Valid data on the DO pins is indicated by RDYON being active. When RDYON is inactive, data on the
DO pins is undefined, and DSON is ignored. The DSON signal acknowledges receiving the data and is used
by the device to internally increment the address counter and output the next location in the buffer. This data
output timing is shown in Figure 10.
Figure 10: Data Output
CLK
DO, ERR
DSON
RDYON
3
3
valid
12
12
valid
12
12
3
3
valid
valid
12
12
12
3
3
valid
12
3
NUMBER
1
2
3
DESCRIPTION
DSON setup time
DSON hold time
DO and RDYON output delay
MINIMUM
10
2
MAXIMUM
15
UNITS
nsec
nsec
nsec
CRTN is valid for an RS block when the first message byte, XK−1, is strobed out of the chip. Figure 11
shows Reverse Order output. In this operation, CRTN is valid on the last byte of the block from the Output
Buffer. In this example only message bytes are output, no check bytes.
Figure 11: CRTN Timing - Reverse Order Output
CLK
DO
DSON
CRTN
RDYON
3
3
Block m
Byte XK-3
12
12
Block m
Byte XK-2
12
12
3
Block m
Byte XK-1
12
12
3 error
VALID
See Note
correctable
3
3
3
Block m+1
Byte X0
12
3
Note: CRTN is active (low) if RS block m is correctable. If the number of errors detected in block m exceeds the
error threshold, P, CRTN is inactive (high).
NUMBER
1
2
3
DESCRIPTION
DSON setup time
DSON hold time
DO and RDYON output delay
MINIMUM
10
2
MAXIMUM
15
UNITS
nsec
nsec
nsec
PS4011C-0200
Page 15 of 24
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