AHA4011C View Datasheet(PDF) - Unspecified
Part Name
Description
Manufacturer
AHA4011C Datasheet PDF : 28 Pages
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Advanced Hardware Architectures, Inc.
Figure 8: Data Input - Buffer Always Ready
CLK
RSTN
DI
12
12
12
12
12
12
12
12
valid
valid
valid
valid
valid
DSIN
ERASE
high = erase
RDYIN
12 12
valid
If RSTN is low during write, message bytes are treated as being part of the initialization sequence. If
RSTN is high, the data is treated as being part of RS block. In the example above ERASE is asserted high
in four sample clocks.
NUMBER
1
2
DESCRIPTION
DI, ERASE and DSIN setup time
DI, ERASE and DSIN hold time
MINIMUM
10
0
MAXIMUM
UNITS
nsec
nsec
Figure 9: Data Input - Buffer Not Ready
CLK
RSTN
DI
12
12
12
valid
12
12
12
12
valid
valid
valid
valid
DSIN
RDYIN
3
3
3
3
NUMBER
1
2
3
DESCRIPTION
DI, ERASE and DSIN setup time
DI, ERASE and DSIN hold time
RDYIN output delay
MINIMUM
10
0
MAXIMUM
15
UNITS
nsec
nsec
nsec
Any input data clocked while RDYIN is inactive are ignored. This is shown in Figure 9.
Page 14 of 24
PS4011C-0200
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