AHA4011C View Datasheet(PDF) - Unspecified
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AHA4011C Datasheet PDF : 28 Pages
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Advanced Hardware Architectures, Inc.
The most common measures of performance for
Reed-Solomon code are PUE, PSE, and CBER. PSE is
the probability of symbol errors and is the ratio of
the number of received symbol errors to the total
number of received symbols. In the AHA4011C
device the symbol length, m, is equal to 8 bits. PUE
is the probability of an uncorrectable error and is the
ratio of the number of uncorrectable code blocks to
the total number of received code blocks. An
uncorrectable error occurs when more than t
received symbols are in error. CBER is the Corrected
Bit Error Rate. The CBER is the reciprocal of
expected number
If input noise
of
is
rcaonrdreocmt b, iCtsBEbRet=wem---Pe----×nU---E--Ne--r.rors.
If PSE = 8 × 10–4 with t = 5 , PUE = 10–7 and
CBER = 8----1-×--0---2–---57---5- = 4.9 × 10–11 .
The figure shows probability of symbol error
and uncorrectable error for block size (N) of 255. It
shows the ability of various levels of Reed-Solomon
error correction to restore the integrity of the
corrupted data. For example, using 255 byte blocks,
if 1 out of 1000 of the received bytes have one or
more bit errors, RS correction with t = 5 will restore
the data to 1 error in 2 million blocks (510 million
bytes).
For a detailed discussion on error rate
performance of Reed-Solomon code, refer to AHA
Application Note, Primer: Reed-Solomon Error
Correction Codes (ECC), (ANRS01).
2.2 DETERMINING DECODER
PERFORMANCE BOUNDARIES
AHA4011C supports a programmable feature
that allows a system designer to determine the
channel performance. This programmable feature,
referred to as error threshold, P, sets a number of
errors to be allowed by the chip prior to flagging the
block uncorrectable. Erasure Rejection Control bit
of the Control Byte register determines the
condition of CRTN output pin.
P and R are both independently selectable by
the user during the Initialization Control Sequence.
The various configurations of P and R are described
as follows:
P > R This is not a sensible choice since this
implies that more check bytes are allocated
for (correction-only) purposes than there
are total check bytes (for both correction
and detection). The device will work as if P
was set equal to R.
P=R
P<R
This configuration maximizes the ability to
correct errors, particularly if R itself has
been chosen to be its maximum value of 20.
This is the usual choice. This situation
causes the CRTN output to flag a message
block as uncorrectable at an error level
exceeding that of which the device is
capable.
This increases the level of error detection
capability. This situation causes the CRTN
output to flag a message block as
uncorrectable at an error level below that of
which the device is capable. This mode
only works with erasures.
Caveat: Output block may be corrupted if a block
exceeds the correction ability of the ECC module.
2.3 ERASURES
The chip is capable of utilizing erasure
information. R erasures may be corrected in any
block assuming there are no unmarked errors.
The correction capability is: E + 2e ≤ R
Where E = number of erasures (marked errors)
e = number of unmarked errors
R = number of check symbols
If there are more than P or R erasures the
erasure information is discarded, and full error
correction is attempted. The chip can be
programmed to either call such a block
uncorrectable or not. If programmed not to call the
block uncorrectable (ERC bit set to 1), the ECC will
utilize the full error correction capability to decide if
the block is correctable.
3.0 OPERATIONAL DESCRIPTION
This section describes the relationship of
associated signals for various functions of the chip.
3.1 CLOCK
The clock input to the chip must meet the timing
requirements shown in Figure 6. The chip is entirely
static thus allowing the clock to stop in either the
active or inactive state for an indefinite period
without loss of stored information.
Page 12 of 24
PS4011C-0200
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