AHA4011C View Datasheet(PDF) - Unspecified
Part Name
Description
Manufacturer
AHA4011C Datasheet PDF : 28 Pages
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Advanced Hardware Architectures, Inc.
C. Start and End of Output
Similar to the burst operation, Output Buffer
may be used to temporarily “hold” data from one
block while the Input Buffer is being filled.
However, these conditions must be satisfied: the
output of a data block must start after the latency
equation (Equation 3) is satisfied, but before the
maximum delay is reached. The maximum delay is:
Equation 4:
maximum_delay=
3
×
N
×
Ci
–
L
×
Co
–
-N-----×-----C----i
Ci – 1
-i-f----m----a---x---i--m----u---m-----_---d---e---l-a---y-
Ci
≥
367,
then
maximum_delay
=
367
×
Ci
i--f----m----a---x---i--m----u---m-----_---d---e---l-a---y-
Ci
>
2
×
N,
then
maximum_delay
=
2
×
N
×
Ci
Data of one block must be fully emptied L × Co
clocks after the start of empty process.
All of the conditions on the maximum delay
given in Equation 4 must be satisfied. If any are not,
the output data stream will begin to inhibit ECC
processing. Eventually this will cause the input
buffer to over fill and RDYIN to become inactive.
Figure 4: Burst and Continuous Operations
(Note: Blocks are shown from right to left as they are input into and output from the chip in Forward Order.
Block i is the first input block, block i + 1 is second input block. XK − 1 is the first input message byte of a block.
Yo is the last input check symbol of a block. Notes 1 and 2 in burst operation are described in Section 2.9.1 Burst
Operation - Caveats.)
Burst Operation
Input Data:
Output Data:
Block i+1
Y0 . . . . . . . . . . X K-1
Block i+1
Y0 . . . . . . . . . . X K-1
1
2
Block i
Y0 . . . . . . . . . . . . . . . . . . X K-1
Block i
Y0 . . . . . . . . . . X K-1
Processing Latency
Continuous Operation
Input Data:
Block i+3
Block i+2
Block i+1
Block i
Y0 . . . . . . . . . . X K-1 Y0 . . . . . . . . . . X K-1 Y0 . . . . . . . . . . X K-1 Y0 . . . . . . . . . . X K-1
Output Data:
Block i+3
Block i+2
Block i+1
Block i
Y0 . . . . . . . . . . X K-1 Y0 . . . . . . . . . . X K-1 Y0 . . . . . . . . . . X K-1 Y0 . . . . . . . . . . X K-1
For a 40 MHz system using the required clocks per byte, maximum latencies and data rates for forward
order output are shown in the table for continuous operation. Input and Output rates are assumed the same
in this table. Note: Other frequency operations are also possible.
Table 3: Continuous Operation Using 40 MHz Clock and Specified Clocks/Byte, Forward
Output Order
CHECK BYTES ‘R’ = 20
CHECK BYTES ‘R’ = 2
BLOCK
LENGTHS ‘N’
MINIMUM
REQUIRED
(clocks/byte)
MAXIMUM
DATA RATE
(MBytes/sec)
MAXIMUM
LATENCY
(µsecs)
MINIMUM
REQUIRED
(clocks/byte)
MAXIMUM
DATA RATE
(MBytes/sec)
MAXIMUM
LATENCY
(µsecs)
25
6
6.67
6.35
5
8
5.33
50
5
8
9.69
5
8
9.24
100
4
10
15.23
4
10
14.78
150
4
10
21.90
4
10
21.45
200
4
10
28.57
4
10
28.12
225
4
10
31.90
4
10
31.45
255
4
10
35.90
4
10
35.45
For Intelsat IESS-308, Rev F, Inner FEC Rates, use Table 4 for a system with 40 MHz clock.
Note: Other frequency operations are also possible.
Page 10 of 24
PS4011C-0200
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