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MPC2104 View Datasheet(PDF) - Motorola => Freescale

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Description
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MPC2104 Datasheet PDF : 24 Pages
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ASYNCHRONOUS DATA RAMs WRITE CYCLE 1 (See Notes 1 and 2)
MPC2107–15
Parameter
Symbol
Min
Max
Unit
Notes
Write Cycle Time
Address Set–up Time
Address Valid to End of Write
Write Pulse Width
tAVAV
15
ns
3
tAVWL
0
ns
tAVWH
12
ns
tWLWH
12
tWLEH
ns
Write Pulse Width, G High
tWLWH
10
ns
4
tWLEH
Data Valid to End of Write
tDVWH
7
ns
Data Hold Time
tWHDX
0
ns
Write Low to Output High–Z
tWLQZ
0
7
ns
5,6,7
Write High to Output Active
tWHQX
5
ns
5,6,7
Write Recovery Time
tWHAX
0
ns
NOTES:
1. A write occurs during the overlap of E low and W low.
2. If E goes low coincident with or after W goes low, the output will remain in a high impedance state.
3. All timings are referenced from the last valid address to the first transitioning address.
4. If E VIH, the output will remain in a high impedance state.
5. At any given voltage and temperature, tWLQZ (max) is less than tWHQX (min), both for a given device and from device to device.
6. Transition is measured ±500 mV from steady–state voltage with load of Figure 1B.
7. This parameter is sampled and not 100% tested.
ASYNCHRONOUS WRITE CYCLE 1 (W Controlled, See Notes 1 and 2)
A (ADDRESS)
E (CHIP ENABLE)
W (WRITE ENABLE)
D (DATA IN)
Q (DATA OUT)
tAVAV
tAVWH
tAVWL
HIGH–Z
tWLQZ
tWLEH
tWLWH
tDVWH
DATA VALID
HIGH–Z
tWHAX
tWHDX
tWHQX
MPC2104MPC2105MPC2106MPC2107
14
MOTOROLA FAST SRAM

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