MPC2104 View Datasheet(PDF) - Motorola => Freescale

Part Name

Description

Manufacturer

MPC2104

256KB and 512KB BurstRAM™ Secondary Cache Modules for PowerPC™ PReP/CHRP Platforms

Motorola => Freescale 

TAG RAM MATCH CYCLE

Parameter

Clock High Write to MATCH Invalid

Clock High Read to MATCH Valid

Address Valid to MATCH Valid

MATCH Valid Hold from Address Change

TOE Low to MATCH Invalid

TOE High to MATCH Valid

TAG RAM RESET (TCLR) CYCLE

Parameter

TCLR Set–up Time

TCLR Hold Time

Status Bit Reset Time

Status Bit Hold from TCLR Low

TCLR Low to MATCH Invalid

TCLR High to MATCH Valid

TCLR Low to TAG High–Z

TCLR High to TAG Active

STANDBY Set–up to TCLR Low

TCLR High to TWE Low

Symbol

tKHML

tKHMV

tAVMV

tAXMX

tGLML

tGHMX

Symbol

tSTC

tHTC

tSRST

tSHRS

tRSML

tRSMV

tRSQZ

tRSQX

tPDSR

tRHWX

Tag RAM

Min

Max

—

7

—

10

—

10

2

—

—

7

—

8

Unit

Notes

ns

ns

ns

ns

ns

ns

Tag RAM

Min

Max

4

—

1

—

—

60

2

—

—

10

—

100

—

10

—

100

30

—

80

—

Unit

Notes

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

OUTPUT

AC TEST LOADS

Z0 = 50 Ω

50 Ω

VL = 1.5 V

OUTPUT

255 Ω

+5 V

480 Ω

5 pF

Figure 1A

Figure 1B

TIMING LIMITS

The table of timing values shows either a

minimum or a maximum limit for each param-

eter. Input requirements are specified from

the external system point of view. Thus, ad-

dress setup time is shown as a minimum

since the system must supply at least that

much time (even though most devices do not

require it). On the other hand, responses from

the memory are specified from the device

point of view. Thus, the access time is shown

as a maximum since the device never pro-

vides data later than that time.

MOTOROLA FAST SRAM

MPC2104•MPC2105•MPC2106•MPC2107

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