MPC2104 View Datasheet(PDF) - Motorola => Freescale

Part Name

Description

Manufacturer

MPC2104

256KB and 512KB BurstRAM™ Secondary Cache Modules for PowerPC™ PReP/CHRP Platforms

Motorola => Freescale 

TAG RAM

RESET FUNCTION TRUTH TABLE (See Notes 1 and 2)

TCLR

L

CLK TWE TAG

L – H H High–Z

VLDout DTYout WTout

L(3)

L(3)

L(3)

L

L–H L

—

—

—

—

NOTES:

1. H = VIH, L = VIL, X = don‘t care, — = unrelated.

2. TOE is X for this table.

MATCH

L(3)

—

TA

High–Z

—

Operation

Reset Status

Not Allowed

POWER

Active

—

READ FUNCTION TRUTH TABLE (See Notes 1, 2, and 3)

TOE TWE CLK TAG VLDin DTYin WTin

L

H

X DOUT

—

—

—

H

X

X High–Z —

—

—

VLDout

—

—

DTYout

—

—

WTout

—

—

MATCH

DOUT

—

Operation

Read Tag I/O

Tag I/O Disable

WRITE FUNCTION TRUTH TABLE (See Notes 1 and 2)

TOE TWE CLK TAG VLDin DTYin WTin VLDout DTYout WTout MATCH

H

L L – H DIN

—

—

—

DOUT DOUT DOUT

L

L

L L–H —

—

—

—

—

—

—

—

NOTES:

1. H = VIH, L = VIL, X = don‘t care, — = unrelated.

2. This table applies when RESET and PWRDN are high.

3. DOUT in this case is the same as DIN. The input data is written through to the outputs during the write operation.

Operation

Write Tag I/O

Not Allowed

MATCH FUNCTION TRUTH TABLE (See Notes 1 through 4)

TOE

TWE

TAG

VLD(4) DTY(4) WT(4)

MATCH

Operation

X

X

—

—

—

—

DOUT

Selected

L

H

DOUT

—

—

—

L

Read Tag I/O

H

L

DIN

DIN

DIN

DIN

L

Write Tag I/O, Status Bits

H

H

TAGIN

L

—

—

L

Invalid Data – Dedicated Status Bits

H

H

TAGIN

H

—

—

M

Match – Dedicated Status Bits

NOTES:

1. H = VIH, L = VIL, X = don‘t care, — = unrelated.

2. M = high if TAGIN equals the memory contents at the address; M = low if TAGIN does not equal the ocntents at that address.

3. PWRDN and RESET are high for this table. OES and CLK are X.

4. This column represents the stored memory cell data for the given status bit at the selected address.

MPC2104•MPC2105•MPC2106•MPC2107

16

MOTOROLA FAST SRAM

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